RISC-V CPU implementation in Amaranth HDL (aka nMigen)
-
Updated
Aug 27, 2024 - Python
RISC-V CPU implementation in Amaranth HDL (aka nMigen)
windows builds of wch openocd fork
A template for running jtag_vpi simulations in vcs
Example project CLion + OpenOCD + Raspberry PI W Zero as OTA flashing probe + Longan Nano(Risc-V) demo board
Openocd for WCH-LinkE with support for multi-WCHLinkE debugging
Add a description, image, and links to the openocd-riscv topic page so that developers can more easily learn about it.
To associate your repository with the openocd-riscv topic, visit your repo's landing page and select "manage topics."