A Parallel Multiplier Using SystemVerilog HDL
-
Updated
Apr 21, 2018 - SystemVerilog
A Parallel Multiplier Using SystemVerilog HDL
32-bit Single Precision Floating point Multiplication
A generic Karatsuba multiplier.
Add a description, image, and links to the multiplier topic page so that developers can more easily learn about it.
To associate your repository with the multiplier topic, visit your repo's landing page and select "manage topics."