5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
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Updated
May 28, 2022 - Verilog
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
Full AES (Verilog)
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
PWM module using verilig HDL in XILINX ISE
This repository contains a few useful Verilog modules
4 bit divider design using first divider algorithm
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