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interrupt: Various improvements #44

Merged
merged 4 commits into from
Oct 19, 2022
Merged

interrupt: Various improvements #44

merged 4 commits into from
Oct 19, 2022

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taiki-e
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@taiki-e taiki-e commented Oct 17, 2022

  • Support RISC-V supervisor mode under portable_atomic_s_mode cfg

    On RISC-V without A-extension, this generates code for machine-mode (M-mode) by default. If you pass the --cfg portable_atomic_s_mode together, this generates code for supervisor-mode (S-mode). In particular, qemu-system-riscv* uses OpenSBI as the default firmware.

  • Support disabling FIQs on pre-v6 ARM under portable_atomic_disable_fiq cfg

    On pre-v6 ARM, this disables only IRQs by default. For many systems (e.g., GBA) this is enough. If the system need to disable both IRQs and FIQs, you need to pass the --cfg portable_atomic_disable_fiq together.

  • Interrupt-related documentation improvements

  • Defer mask until just before branch

    This does not change the code generation, but in the actual generated code the mask is deferred until just before the branch, like this. Since there has been some misleading discussion about this in the past, we will use code that more closely matches the generated code.

    For MSP430 and AVR, it will be done in interrupt: Optimize restore on AVR and MSP430 #40.

@taiki-e taiki-e added O-arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state O-riscv Target: RISC-V architecture O-avr Target: AVR labels Oct 17, 2022
Under portable_atomic_s_mode cfg.
Under portable_atomic_disable_fiq cfg.
This does not change the code generation, but in the actual generated
code the mask is deferred until just before the branch, like this.
Since there has been some misleading discussion about this in the past,
we will use code that more closely matches the generated code.
@taiki-e taiki-e added the C-documentation Category: related to documentation. label Oct 19, 2022
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taiki-e commented Oct 19, 2022

bors r+

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bors bot commented Oct 19, 2022

@bors bors bot merged commit c62df36 into main Oct 19, 2022
@bors bors bot deleted the interrupt2 branch October 19, 2022 15:09
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C-documentation Category: related to documentation. O-arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state O-riscv Target: RISC-V architecture
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