Optimize pre-v6 ARM load/store on single-core systems #36
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Yeah this basically sounds like what i was fighting with earlier today. |
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Hmm, in release mode it is fine, but in debug mode it fails to compile due to the compiler cannot remove dead code: https://github.com/taiki-e/portable-atomic/runs/8173770404?check_suite_focus=true I should use inline asm for load/store as well like #18. |
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36: Optimize pre-v6 ARM load/store on single-core systems r=taiki-e a=taiki-e Since pre-v6[^v6] ARM has no Data Memory Barrier and cannot implement atomic in a way compatible with v6 and later multicore CPUs without OS helpers, LLVM generates libcalls for atomic operations that require synchronization, such as Acquire/Release and SeqCst. Currently, (when `portable_atomic_unsafe_assume_single_core` cfg is used) we consider this as "atomic load/store are not available on pre-v6 ARM" and always disable interrupts. However, relaxed load+compiler fence can do this more efficiently since we know it is single-core. https://github.com/taiki-e/portable-atomic/blob/e6e1500f440e6a79d87f4471924c5e6613594b51/src/imp/interrupt/mod.rs#L34-L35 https://github.com/taiki-e/portable-atomic/blob/e6e1500f440e6a79d87f4471924c5e6613594b51/src/imp/interrupt/mod.rs#L23-L29 FYI `@Lokathor` [^v6]: ARMv6 except for ARMv6-M also does not have the DMB instruction, but there is [a special instruction equivalent to DMB](https://developer.arm.com/documentation/ddi0360/e/control-coprocessor-cp15/register-descriptions/c7--cache-operations-register?lang=en). Co-authored-by: Taiki Endo <te316e89@gmail.com>
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36: Optimize pre-v6 ARM load/store on single-core systems r=taiki-e a=taiki-e Since pre-v6[^v6] ARM has no Data Memory Barrier and cannot implement atomic in a way compatible with v6 and later multicore CPUs without OS helpers, LLVM generates libcalls for atomic operations that require synchronization, such as Acquire/Release and SeqCst. Currently, (when `portable_atomic_unsafe_assume_single_core` cfg is used) we consider this as "atomic load/store are not available on pre-v6 ARM" and always disable interrupts. However, relaxed load+compiler fence can do this more efficiently since we know it is single-core. https://github.com/taiki-e/portable-atomic/blob/e6e1500f440e6a79d87f4471924c5e6613594b51/src/imp/interrupt/mod.rs#L34-L35 https://github.com/taiki-e/portable-atomic/blob/e6e1500f440e6a79d87f4471924c5e6613594b51/src/imp/interrupt/mod.rs#L23-L29 FYI `@Lokathor` [^v6]: ARMv6 except for ARMv6-M also does not have the DMB instruction, but there is [a special instruction equivalent to DMB](https://developer.arm.com/documentation/ddi0360/e/control-coprocessor-cp15/register-descriptions/c7--cache-operations-register?lang=en). Co-authored-by: Taiki Endo <te316e89@gmail.com>
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Since pre-v61 ARM has no Data Memory Barrier and cannot implement atomic in a way compatible with v6 and later multicore CPUs without OS helpers, LLVM generates libcalls for atomic operations that require synchronization, such as Acquire/Release and SeqCst.
Currently, (when
portable_atomic_unsafe_assume_single_corecfg is used) we consider this as "atomic load/store are not available on pre-v6 ARM" and always disable interrupts. However, relaxed load+compiler fence can do this more efficiently since we know it is single-core.portable-atomic/src/imp/interrupt/mod.rs
Lines 34 to 35 in e6e1500
portable-atomic/src/imp/interrupt/mod.rs
Lines 23 to 29 in e6e1500
FYI @Lokathor
Footnotes
ARMv6 except for ARMv6-M also does not have the DMB instruction, but there is a special instruction equivalent to DMB. ↩