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6. Basic wiring
sy2002 edited this page Jul 11, 2022
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TODO:
- Describe how to do a basic wiring of the MiSTer core in main.vhd, which includes a VGA out, so that people can see a first "vital sign" of the running core
- Describe pitfalls: ROM and ROM loading, RAM and RAM timing (address latching necessary?), Low-Active vs. High-Active when setting unused input ports (link to some of the C64 bugs/examples)
- Describe clocking and the fact that the exact speed needs to be provided within a global constant
- Decision about replacing RAM/ROM instantiation within the MiSTer source code (done in C64) or try to define components with the same name and interface and then let the MiSTer core use this component