Zero Conf implementation details

Zero conf

This article details how HDL Code Checker implements elements of auto project layout inference, aka zero configuration.

The idea is to solve most ambiguities or at least allow the user to hint and so the tool can sort the rest on its own.

The basics are:

1. Infer which library a given source should be compiled into (VHDL only)
2. Inter which includes should be set for Verilog and SystemVerilog files
3. Inter flags?
4. Work out the compilation sequence

Experimental, none of this has not made into the master just yet

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Library inference

HDL Code Checker can infer libraries for sources whose library hasn't been set. To do that, it does what one would manually do: search files.

Library inference -- Quick

This is intended to infer libraries by just looking at design units defined on a path and how they're used, which should work in most projects.

1. Given a path, find all design units it defines
2. For every design unit, check how they are used throughout the code base
   1. List all explicit uses of the name of the design unit
   2. Extract the library it refers to, but ignore "work"
3. List unique library names referred and check if
   1. There is no unique names, i.e., design units on a given source are never used anywhere
      In this case, use "work"? Or maybe a temporary name? Delete library afterwards to avoid messing up?
   2. All uses converge on a single name
      Use the given name as library
   3. There's multiple unique names, use library inference full

Library inference -- Full

This is a fallback method for cases where the quick algorithm fails. It's intended to be accurate rather than fast.

This should ideally solve corner cases such as projects defining a design unit with the same name but different implementations (and likely different libraries).

Consider an environment where components are divided into libraries and all libraries have a package named config that has library wide configuration parameters. In this setup, foo.config and bar.config refer to different packages compiled into different libraries (and defined in different files).

Build sequence

Determines the build sequence of a given source.

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Misc

Design unit

Design unit in this context actually mean "design units we're interested", which include

• Entity declarations
• Package declarations (not package bodies)
• Context declarations

Might be better to use a better name to a avoid clashing with the VHDL spec.

Explicit uses

Right now only explicit uses are counted, i.e.,

library foo;
use foo.some_package; -- This will be counted
use foo.all;          -- This will NOT be counted
...

architecture foo of bar
...
begin

  entity_that_counts_u : entity foo.some_entity -- This will be counted
  ...
  entity_that_doesnt_count_u: some_component -- This will NOT be counted
  ...
end architecture foo;