merged with main

strath-sdr · Mar 12, 2021 · 69289af · 69289af
2 parents be51ee5 + 0b5c7bd
commit 69289af
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Showing 3 changed files with 77 additions and 3 deletions.
diff --git a/rfsoc_freqplan/application.py b/rfsoc_freqplan/application.py
@@ -4,11 +4,13 @@
 
 from .interface import ADCWidgets, DACWidgets, DDCWidgets, DUCWidgets
 import ipywidgets as widgets
+from pkg_resources import resource_stream
 
 class FrequencyPlannerApplication:
     def __init__(self):
-        with open('info.html', 'r') as f:
-            info = widgets.HTML(value=f.read())
+        f = resource_stream('rfsoc_freqplan', 'info.html')
+        info = widgets.HTML(value=f.read())
+        f.close()
 
         adc = ADCWidgets().layout
         dac = DACWidgets().layout

diff --git a/rfsoc_freqplan/info.html b/rfsoc_freqplan/info.html
@@ -0,0 +1,72 @@
+<html>
+
+<style>a{color: #3366BB;}</style>
+<style>h3{padding:0px; margin:0px }</style>
+<style>
+      table {
+        border-collapse: collapse;
+      }
+      td,
+      th {
+        padding: 5px;
+        text-align: left;
+      }
+    </style>
+
+<body>
+
+<h3>Abbreviations and Acronyms</h3>
+
+<table border="1" width="auto">
+<thead>
+<tr>
+<th>Name</th>
+<th>Description</th>
+</tr>
+<tr>
+<td><strong>Fc</strong></td>
+<td>Centre frequency</td>
+</tr>
+</thead>
+<tbody>
+<tr>
+<td><strong>Fs</strong></td>
+<td>Sample Rate</td>
+</tr>
+<tr>
+<td><strong>GTIS</strong></td>
+<td>Gain/time interleaving spur</td>
+</tr>
+<tr>
+<td><strong>HD</strong></td>
+<td>Harmonic frequency</td>
+</tr>
+<tr>
+<td><strong>IL</strong></td>
+<td>Interleaving</td>
+</tr>
+<tr>
+<td><strong>NCO</strong></td>
+<td>Numerically Controlled Oscillator</td>
+</tr>
+<tr>
+<td>NSD</td>
+<td>Noise Spectral Density</td>
+</tr>
+<tr>
+<td><strong>OIS</strong></td>
+<td>Offset interleaving spur</td>
+</tr>
+<tr>
+<td><strong>PLL</strong></td>
+<td>Phase-Locked Loop</td>
+</tr>
+</tbody>
+</table>
+
+<br>
+<h3>Spur Amplitudes</h3>
+<p>Typical values for the spur amplitudes used in the DDC and DUC planners can be found in the RFSoC datasheet <a href="https://www.xilinx.com/support/documentation/data_sheets/ds926-zynq-ultrascale-plus-rfsoc.pdf" target="_blank" rel="noopener noreferrer">DS926</a>.</p>
+
+</body>
+</html>
diff --git a/setup.py b/setup.py
@@ -7,7 +7,7 @@
 # global variables
 package_name = 'rfsoc_freqplan'
 pip_name = 'rfsoc-freqplan'
-data_files = []
+data_files = ['info.html']
 
 # heroku setup
 if os.path.isfile('Procfile'):