🧪 Add experimental XBUS (Wishbone) to AHB3-Lite bridge

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 03.07.2024 | 1.10.0.8 | :test_tube: add XBUS to AHB3-lite bridge | [#937](https://github.com/stnolting/neorv32/pull/937) |
 | 02.07.2024 | 1.10.0.7 | minor rtl and software edits and cleanups | [#936](https://github.com/stnolting/neorv32/pull/936) |
 | 30.06.2024 | 1.10.0.6 | minor rtl edits and cleanups | [#935](https://github.com/stnolting/neorv32/pull/935) |
 | 29.06.2024 | 1.10.0.5 | :warning: rework and optimize custom functions unit (CFU) interface; simplified illegal RVC decoding | [#932](https://github.com/stnolting/neorv32/pull/932) |

docs/datasheet/overview.adoc

@@ -141,7 +141,7 @@ neorv32               - Project home folder
 │├core                - Core sources of the CPU & SoC
 ││└mem                - SoC-internal memories (default architectures)
 │├processor_templates - Pre-configured SoC wrappers
-│├system_integration  - System wrappers for advanced connectivity
+│├system_integration  - System wrappers and bridges for advanced connectivity
 │└test_setups         - Minimal test setup "SoCs" used in the User Guide
 │
 ├sim                  - Simulation files (see User Guide)

docs/datasheet/soc_xbus.adoc

@@ -41,12 +41,17 @@ The external interface is **not** mapped to a specific address space. Instead, a
 do not target a specific (and actually implemented) processor-internal address region (hence, accessing the "void";
 see section <<_address_space>>) are **redirected** to the external bus interface.
 
-.AXI4-Lite Interface
+.AXI4-Lite Interface Bridge
 [TIP]
 A processor top entity with an AXI4-Lite-compatible bus interface can be found in `rtl/system_inegration`.
 More information regarding this alternate top entity can be found in in the user guide:
 https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block
 
+.AHB3-Lite Interface Bridge
+[TIP]
+A simple bridge that converts the processor's XBUS into an AHB3-lite-compatible host interface can
+be found in in `rtl/system_inegration` (`xbus2ahblite_bridge.vhd`).
+
 
 **Wishbone Bus Protocol**
 

docs/legal.adoc

@@ -58,7 +58,7 @@ OF THE POSSIBILITY OF SUCH DAMAGE.
 
 * "GitHub" is a Subsidiary of Microsoft Corporation.
 * "Vivado" and "Artix" are trademarks of AMD Inc.
-* "AXI", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
+* "AXI", "AXI", "AXI4-Lite", "AXI4-Stream", "AHB", "AHB3" and "AHB3-Lite" are trademarks of Arm Holdings plc.
 * "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
 * "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.
 * "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100007"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100008"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

rtl/system_integration/README.md

@@ -2,25 +2,32 @@
 
 ### `neorv32_litex_core_complex.vhd`
 
-Pre-configured top entity wrapper for integration within the [LiteX](https://github.com/enjoy-digital/litex) SoC builder framework.
-This wrapper provides AXI4-Lite- and AXI4-Stream-compatible interfaces.
+Pre-configured top entity wrapper for integration within the [LiteX](https://github.com/enjoy-digital/litex)
+SoC builder framework. This wrapper provides AXI4-Lite- and AXI4-Stream-compatible interfaces.
 
 > [!TIP]
-> See the user guide section [`core/mem`](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) for more information.
+> See the user guide section [`core/mem`](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support)
+for more information.
 
 > [!NOTE]
 > The provided top entity wrapper can also be used for custom (AXI) setups outside of Vivado IP block designs.
 
 
 ### `neorv32_vivado_ip.vhd`
 
-Processor top entity with optional AXI4-Lite and AXI4-Stream interfaces. Dedicated for integration as custom IP block within AMD Vivado.
-Run the provided packaging script in the Vivado TCL shell to generate a NEORV32 IP block:
+Processor top entity with optional AXI4-Lite and AXI4-Stream interfaces. Dedicated for integration as custom
+IP block within AMD Vivado. Run the provided packaging script in the Vivado TCL shell to generate a NEORV32
+IP block:
 
 ```tcl
 source neorv32_vivado_ip.tcl
 ```
 
 > [!TIP]
 > See the user guide's [UG: Packaging the Processor as Vivado IP Block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block)
-section for more information and step-by-step instructions for generating a NEORV32 IP module.
+section for more information and step-by-step instructions for generating a NEORV32 IP module.
+
+
+### `xbus2ahblite_bridge.vhd`
+
+A simple bridge module that converts the processor's XBUS interface into an AHB3-lite-compatible host interface.

rtl/system_integration/xbus2ahblite_bridge.vhd

@@ -0,0 +1,108 @@
+-- ================================================================================ --
+-- NEORV32 SoC - XBUS to AHB3-Lite Bridge (non-overlapping single transfers only)   --
+-- -------------------------------------------------------------------------------- --
+-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
+-- Copyright (c) NEORV32 contributors.                                              --
+-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  --
+-- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
+-- SPDX-License-Identifier: BSD-3-Clause                                            --
+-- ================================================================================ --
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity xbus2ahblite_bridge is
+  port (
+    -- global control --
+    clk_i        : in  std_ulogic;                     -- global clock line
+    rstn_i       : in  std_ulogic;                     -- global reset line, low-active, use as async
+    -- xbus device interface --
+    xbus_adr_i   : in  std_ulogic_vector(31 downto 0); -- address
+    xbus_dat_i   : in  std_ulogic_vector(31 downto 0); -- write data
+    xbus_tag_i   : in  std_ulogic_vector(2 downto 0);  -- access tag
+    xbus_we_i    : in  std_ulogic;                     -- read/write
+    xbus_sel_i   : in  std_ulogic_vector(3 downto 0);  -- byte enable
+    xbus_stb_i   : in  std_ulogic;                     -- strobe
+    xbus_cyc_i   : in  std_ulogic;                     -- valid cycle
+    xbus_ack_o   : out std_ulogic;                     -- transfer acknowledge
+    xbus_err_o   : out std_ulogic;                     -- transfer error
+    xbus_dat_o   : out std_ulogic_vector(31 downto 0); -- read data
+    -- ahb-lite host interface --
+    ahb_haddr_o  : out std_ulogic_vector(31 downto 0); -- address
+    ahb_hwdata_o : out std_ulogic_vector(31 downto 0); -- write data
+    ahb_hwrite_o : out std_ulogic;                     -- read/write
+    ahb_hsize_o  : out std_ulogic_vector(2 downto 0);  -- transfer size
+    ahb_hburst_o : out std_ulogic_vector(2 downto 0);  -- burst type
+    ahb_hprot_o  : out std_ulogic_vector(3 downto 0);  -- protection control
+    ahb_htrans_o : out std_ulogic_vector(1 downto 0);  -- transfer type
+    ahb_hready_i : in  std_ulogic;                     -- transfer completed
+    ahb_hresp_i  : in  std_ulogic;                     -- transfer response
+    ahb_hrdata_i : in  std_ulogic_vector(31 downto 0)  -- read data
+  );
+end xbus2ahblite_bridge;
+
+architecture xbus2ahblite_bridge_rtl of xbus2ahblite_bridge is
+
+  -- arbiter --
+  signal addr_ack_q : std_ulogic; -- address phase transfer completed
+  signal pending_q  : std_ulogic; -- pending bus transaction (bus is in "data phase")
+
+begin
+
+  -- access arbiter --
+  arbiter: process(rstn_i, clk_i)
+  begin
+    if (rstn_i = '0') then
+      addr_ack_q <= '0';
+      pending_q  <= '0';
+    elsif rising_edge(clk_i) then
+      if (pending_q = '0') then -- idle (also AHB address phase)
+        addr_ack_q <= ahb_hready_i; -- sample HREADY in address phase
+        if (xbus_stb_i = '1') then
+          pending_q <= '1';
+        end if;
+      else -- transfer in progress (AHB data phase)
+        -- complete if HREADY has acknowledged address phase and is acknowledging data phase
+        -- abort if core terminated the transfer by pulling CYC low
+        if ((addr_ack_q = '1') and (ahb_hready_i = '1')) or (xbus_cyc_i = '0') then
+          addr_ack_q <= '0';
+          pending_q  <= '0';
+        end if;
+      end if;
+    end if;
+  end process arbiter;
+
+  -- host response: evaluate in data phase --
+  xbus_ack_o <= '1' when (addr_ack_q = '1') and (pending_q = '1') and (ahb_hready_i = '1') and (ahb_hresp_i = '0') else '0'; -- okay
+  xbus_err_o <= '1' when (addr_ack_q = '1') and (pending_q = '1') and (ahb_hready_i = '1') and (ahb_hresp_i = '1') else '0'; -- error
+
+  -- host request: NONSEQ during address phase, IDLE during data phase --
+  ahb_htrans_o <= "10" when (xbus_stb_i = '1') else "00";
+
+  -- protection control --
+  ahb_hprot_o(3) <= '0'; -- non-cacheable
+  ahb_hprot_o(2) <= '0'; -- non-bufferable
+  ahb_hprot_o(1) <= xbus_tag_i(0); -- 0 = user-access, 1 = privileged access
+  ahb_hprot_o(0) <= not xbus_tag_i(2); -- 0 = instruction fetch, 1 = data access
+
+  -- burst control --
+  ahb_hburst_o <= "000"; -- single burst
+
+  -- read/write --
+  ahb_hwrite_o <= xbus_we_i;
+
+  -- address --
+  ahb_haddr_o <= xbus_adr_i;
+
+  -- data --
+  ahb_hwdata_o <= xbus_dat_i;
+  xbus_dat_o   <= ahb_hrdata_i;
+
+  -- data quantity --
+  with xbus_sel_i select ahb_hsize_o <=
+    "000" when "1000" | "0100" | "0010" | "0001", -- byte
+    "001" when "1100" | "0011", -- half-word (aligned only)
+    "010" when others; -- word
+
+end xbus2ahblite_bridge_rtl;

sim/neorv32_tb.vhd

@@ -107,8 +107,9 @@ architecture neorv32_tb_rtl of neorv32_tb is
     addr  : std_ulogic_vector(31 downto 0); -- address
     wdata : std_ulogic_vector(31 downto 0); -- master write data
     rdata : std_ulogic_vector(31 downto 0); -- master read data
+    tag   : std_ulogic_vector(2 downto 0); -- access tag
     we    : std_ulogic; -- write enable
-    sel   : std_ulogic_vector(03 downto 0); -- byte enable
+    sel   : std_ulogic_vector(3 downto 0); -- byte enable
     stb   : std_ulogic; -- strobe
     cyc   : std_ulogic; -- valid cycle
     ack   : std_ulogic; -- transfer acknowledge
@@ -294,7 +295,7 @@ begin
     -- External bus interface (available if XBUS_EN = true) --
     xbus_adr_o     => wb_cpu.addr,     -- address
     xbus_dat_o     => wb_cpu.wdata,    -- write data
-    xbus_tag_o     => open,            -- access tag
+    xbus_tag_o     => wb_cpu.tag,      -- access tag
     xbus_we_o      => wb_cpu.we,       -- read/write
     xbus_sel_o     => wb_cpu.sel,      -- byte enable
     xbus_stb_o     => wb_cpu.stb,      -- strobe

sim/simple/neorv32_tb.simple.vhd

@@ -127,8 +127,9 @@ architecture neorv32_tb_simple_rtl of neorv32_tb_simple is
     addr  : std_ulogic_vector(31 downto 0); -- address
     wdata : std_ulogic_vector(31 downto 0); -- master write data
     rdata : std_ulogic_vector(31 downto 0); -- master read data
+    tag   : std_ulogic_vector(2 downto 0); -- access tag
     we    : std_ulogic; -- write enable
-    sel   : std_ulogic_vector(03 downto 0); -- byte enable
+    sel   : std_ulogic_vector(3 downto 0); -- byte enable
     stb   : std_ulogic; -- strobe
     cyc   : std_ulogic; -- valid cycle
     ack   : std_ulogic; -- transfer acknowledge
@@ -270,7 +271,7 @@ begin
     -- External bus interface (available if XBUS_EN = true) --
     xbus_adr_o     => wb_cpu.addr,     -- address
     xbus_dat_o     => wb_cpu.wdata,    -- write data
-    xbus_tag_o     => open,            -- access tag
+    xbus_tag_o     => wb_cpu.tag,      -- access tag
     xbus_we_o      => wb_cpu.we,       -- read/write
     xbus_sel_o     => wb_cpu.sel,      -- byte enable
     xbus_stb_o     => wb_cpu.stb,      -- strobe