Minor sw & hw cleanups

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 02.07.2024 | 1.10.0.7 | minor rtl and software edits and cleanups | [#936](https://github.com/stnolting/neorv32/pull/936) |
 | 30.06.2024 | 1.10.0.6 | minor rtl edits and cleanups | [#935](https://github.com/stnolting/neorv32/pull/935) |
 | 29.06.2024 | 1.10.0.5 | :warning: rework and optimize custom functions unit (CFU) interface; simplified illegal RVC decoding | [#932](https://github.com/stnolting/neorv32/pull/932) |
 | 23.06.2024 | 1.10.0.4 | minor rtl edits/cleanups | [#931](https://github.com/stnolting/neorv32/pull/931) |

docs/datasheet/software.adoc

@@ -94,7 +94,8 @@ The NEORV32 project provides a set of pre-defined C libraries that allow an easy
 | `neorv32_dma.c`     | `neorv32_dma.h`        | <<_direct_memory_access_controller_dma>> HAL
 | `neorv32_gpio.c`    | `neorv32_gpio.h`       | <<_general_purpose_input_and_output_port_gpio>> HAL
 | `neorv32_gptmr.c`   | `neorv32_gptmr.h`      | <<_general_purpose_timer_gptmr>> HAL
-| -                   | `neorv32_intrinsics.h` | Macros for intrinsics & custom instructions
+| -                   | `neorv32_intrinsics.h` | Macros for intrinsics and custom instructions
+| -                   | `neorv32_legacy.h`     | Legacy compatibility layer / wrappers (**do not use for new designs!**)
 | `neorv32_mtime.c`   | `neorv32_mtime.h`      | <<_machine_system_timer_mtime>> HAL
 | `neorv32_neoled.c`  | `neorv32_neoled.h`     | <<_smart_led_interface_neoled>> HAL
 | `neorv32_onewire.c` | `neorv32_onewire.h`    | <<_one_wire_serial_interface_controller_onewire>> HAL

rtl/core/neorv32_cpu_cp_cfu.vhd

@@ -111,9 +111,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-library neorv32;
-use neorv32.neorv32_package.all;
-
 entity neorv32_cpu_cp_cfu is
   port (
     -- global control --
@@ -251,12 +248,7 @@ begin
   -- -------------------------------------------------------------------------------------------
   result_select: process(rtype_i, funct3_i, xtea)
   begin
-    -- defaults --
-    result_o <= (others => '0');
-    valid_o  <= '0';
-
-    -- check instruction type --
-    case rtype_i is
+    case rtype_i is -- check instruction type
 
       when r3type_c => -- R3-type instructions; function select via "funct3" and ""funct7
       -- ----------------------------------------------------------------------

rtl/core/neorv32_intercon.vhd

@@ -396,7 +396,18 @@ entity neorv32_bus_io_switch is
     DEV_17_EN : boolean; DEV_17_BASE : std_ulogic_vector(31 downto 0);
     DEV_18_EN : boolean; DEV_18_BASE : std_ulogic_vector(31 downto 0);
     DEV_19_EN : boolean; DEV_19_BASE : std_ulogic_vector(31 downto 0);
-    DEV_20_EN : boolean; DEV_20_BASE : std_ulogic_vector(31 downto 0)
+    DEV_20_EN : boolean; DEV_20_BASE : std_ulogic_vector(31 downto 0);
+    DEV_21_EN : boolean; DEV_21_BASE : std_ulogic_vector(31 downto 0);
+    DEV_22_EN : boolean; DEV_22_BASE : std_ulogic_vector(31 downto 0);
+    DEV_23_EN : boolean; DEV_23_BASE : std_ulogic_vector(31 downto 0);
+    DEV_24_EN : boolean; DEV_24_BASE : std_ulogic_vector(31 downto 0);
+    DEV_25_EN : boolean; DEV_25_BASE : std_ulogic_vector(31 downto 0);
+    DEV_26_EN : boolean; DEV_26_BASE : std_ulogic_vector(31 downto 0);
+    DEV_27_EN : boolean; DEV_27_BASE : std_ulogic_vector(31 downto 0);
+    DEV_28_EN : boolean; DEV_28_BASE : std_ulogic_vector(31 downto 0);
+    DEV_29_EN : boolean; DEV_29_BASE : std_ulogic_vector(31 downto 0);
+    DEV_30_EN : boolean; DEV_30_BASE : std_ulogic_vector(31 downto 0);
+    DEV_31_EN : boolean; DEV_31_BASE : std_ulogic_vector(31 downto 0)
   );
   port (
     -- host port --
@@ -423,56 +434,51 @@ entity neorv32_bus_io_switch is
     dev_17_req_o : out bus_req_t; dev_17_rsp_i : in bus_rsp_t;
     dev_18_req_o : out bus_req_t; dev_18_rsp_i : in bus_rsp_t;
     dev_19_req_o : out bus_req_t; dev_19_rsp_i : in bus_rsp_t;
-    dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t
+    dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t;
+    dev_21_req_o : out bus_req_t; dev_21_rsp_i : in bus_rsp_t;
+    dev_22_req_o : out bus_req_t; dev_22_rsp_i : in bus_rsp_t;
+    dev_23_req_o : out bus_req_t; dev_23_rsp_i : in bus_rsp_t;
+    dev_24_req_o : out bus_req_t; dev_24_rsp_i : in bus_rsp_t;
+    dev_25_req_o : out bus_req_t; dev_25_rsp_i : in bus_rsp_t;
+    dev_26_req_o : out bus_req_t; dev_26_rsp_i : in bus_rsp_t;
+    dev_27_req_o : out bus_req_t; dev_27_rsp_i : in bus_rsp_t;
+    dev_28_req_o : out bus_req_t; dev_28_rsp_i : in bus_rsp_t;
+    dev_29_req_o : out bus_req_t; dev_29_rsp_i : in bus_rsp_t;
+    dev_30_req_o : out bus_req_t; dev_30_rsp_i : in bus_rsp_t;
+    dev_31_req_o : out bus_req_t; dev_31_rsp_i : in bus_rsp_t
   );
 end neorv32_bus_io_switch;
 
 architecture neorv32_bus_io_switch_rtl of neorv32_bus_io_switch is
 
-  -- ------------------------------------------------------------------------------------------- --
-  -- How to add another device port                                                              --
-  -- ------------------------------------------------------------------------------------------- --
-  -- 1. Increment <num_devs_physical_c> (must not exceed <num_devs_logical_c>).                  --
-  -- 2. Append another pair of "DEV_xx_EN" and "DEV_xx_BASE" generics.                           --
-  -- 3. Append these two generics to the according <dev_en_list_c> and <dev_base_list_c> arrays. --
-  -- 4. Append another pair of "dev_xx_req_o" and "dev_xx_rsp_i" ports.                          --
-  -- 5. Append these two ports to the according <dev_req> and <dev_rsp> array assignments in     --
-  --    the "Combine Device Ports" section.                                                      --
-  -- ------------------------------------------------------------------------------------------- --
-
   -- module configuration --
-  constant num_devs_physical_c : natural := 21; -- actual number of devices, max num_devs_logical_c
-  constant num_devs_logical_c  : natural := 32; -- logical max number of devices; do not change!
+  constant num_devs_c : natural := 32; -- number of device ports
 
   -- address bits for access decoding --
   constant abb_lo_c : natural := index_size_f(DEV_SIZE); -- low address boundary bit
-  constant abb_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_logical_c)) - 1; -- high address boundary bit
+  constant abb_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_c)) - 1; -- high address boundary bit
 
   -- list of enabled device ports --
-  type dev_en_list_t is array (0 to num_devs_physical_c-1) of boolean;
+  type dev_en_list_t is array (0 to num_devs_c-1) of boolean;
   constant dev_en_list_c : dev_en_list_t := (
-    DEV_00_EN, DEV_01_EN, DEV_02_EN, DEV_03_EN,
-    DEV_04_EN, DEV_05_EN, DEV_06_EN, DEV_07_EN,
-    DEV_08_EN, DEV_09_EN, DEV_10_EN, DEV_11_EN,
-    DEV_12_EN, DEV_13_EN, DEV_14_EN, DEV_15_EN,
-    DEV_16_EN, DEV_17_EN, DEV_18_EN, DEV_19_EN,
-    DEV_20_EN
+    DEV_00_EN, DEV_01_EN, DEV_02_EN, DEV_03_EN, DEV_04_EN, DEV_05_EN, DEV_06_EN, DEV_07_EN,
+    DEV_08_EN, DEV_09_EN, DEV_10_EN, DEV_11_EN, DEV_12_EN, DEV_13_EN, DEV_14_EN, DEV_15_EN,
+    DEV_16_EN, DEV_17_EN, DEV_18_EN, DEV_19_EN, DEV_20_EN, DEV_21_EN, DEV_22_EN, DEV_23_EN,
+    DEV_24_EN, DEV_25_EN, DEV_26_EN, DEV_27_EN, DEV_28_EN, DEV_29_EN, DEV_30_EN, DEV_31_EN
   );
 
   -- list of device base addresses --
-  type dev_base_list_t is array (0 to num_devs_physical_c-1) of std_ulogic_vector(31 downto 0);
+  type dev_base_list_t is array (0 to num_devs_c-1) of std_ulogic_vector(31 downto 0);
   constant dev_base_list_c : dev_base_list_t := (
-    DEV_00_BASE, DEV_01_BASE, DEV_02_BASE, DEV_03_BASE,
-    DEV_04_BASE, DEV_05_BASE, DEV_06_BASE, DEV_07_BASE,
-    DEV_08_BASE, DEV_09_BASE, DEV_10_BASE, DEV_11_BASE,
-    DEV_12_BASE, DEV_13_BASE, DEV_14_BASE, DEV_15_BASE,
-    DEV_16_BASE, DEV_17_BASE, DEV_18_BASE, DEV_19_BASE,
-    DEV_20_BASE
+    DEV_00_BASE, DEV_01_BASE, DEV_02_BASE, DEV_03_BASE, DEV_04_BASE, DEV_05_BASE, DEV_06_BASE, DEV_07_BASE,
+    DEV_08_BASE, DEV_09_BASE, DEV_10_BASE, DEV_11_BASE, DEV_12_BASE, DEV_13_BASE, DEV_14_BASE, DEV_15_BASE,
+    DEV_16_BASE, DEV_17_BASE, DEV_18_BASE, DEV_19_BASE, DEV_20_BASE, DEV_21_BASE, DEV_22_BASE, DEV_23_BASE,
+    DEV_24_BASE, DEV_25_BASE, DEV_26_BASE, DEV_27_BASE, DEV_28_BASE, DEV_29_BASE, DEV_30_BASE, DEV_31_BASE
   );
 
   -- device ports combined as arrays --
-  type dev_req_t is array (0 to num_devs_physical_c-1) of bus_req_t;
-  type dev_rsp_t is array (0 to num_devs_physical_c-1) of bus_rsp_t;
+  type dev_req_t is array (0 to num_devs_c-1) of bus_req_t;
+  type dev_rsp_t is array (0 to num_devs_c-1) of bus_rsp_t;
   signal dev_req : dev_req_t;
   signal dev_rsp : dev_rsp_t;
 
@@ -501,20 +507,31 @@ begin
   dev_18_req_o <= dev_req(18); dev_rsp(18) <= dev_18_rsp_i;
   dev_19_req_o <= dev_req(19); dev_rsp(19) <= dev_19_rsp_i;
   dev_20_req_o <= dev_req(20); dev_rsp(20) <= dev_20_rsp_i;
+  dev_21_req_o <= dev_req(21); dev_rsp(21) <= dev_21_rsp_i;
+  dev_22_req_o <= dev_req(22); dev_rsp(22) <= dev_22_rsp_i;
+  dev_23_req_o <= dev_req(23); dev_rsp(23) <= dev_23_rsp_i;
+  dev_24_req_o <= dev_req(24); dev_rsp(24) <= dev_24_rsp_i;
+  dev_25_req_o <= dev_req(25); dev_rsp(25) <= dev_25_rsp_i;
+  dev_26_req_o <= dev_req(26); dev_rsp(26) <= dev_26_rsp_i;
+  dev_27_req_o <= dev_req(27); dev_rsp(27) <= dev_27_rsp_i;
+  dev_28_req_o <= dev_req(28); dev_rsp(28) <= dev_28_rsp_i;
+  dev_29_req_o <= dev_req(29); dev_rsp(29) <= dev_29_rsp_i;
+  dev_30_req_o <= dev_req(30); dev_rsp(30) <= dev_30_rsp_i;
+  dev_31_req_o <= dev_req(31); dev_rsp(31) <= dev_31_rsp_i;
 
 
   -- Request --------------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   bus_request_gen:
-  for i in 0 to (num_devs_physical_c-1) generate
+  for i in 0 to (num_devs_c-1) generate
 
     bus_request_port_enabled:
     if dev_en_list_c(i) generate
       bus_request: process(main_req_i)
       begin
         dev_req(i) <= main_req_i;
         if (main_req_i.addr(abb_hi_c downto abb_lo_c) = dev_base_list_c(i)(abb_hi_c downto abb_lo_c)) then
-          dev_req(i).stb <= main_req_i.stb;
+          dev_req(i).stb <= main_req_i.stb; -- propagate transaction strobe if address match
         else
           dev_req(i).stb <= '0';
         end if;
@@ -526,7 +543,7 @@ begin
       dev_req(i) <= req_terminate_c;
     end generate;
 
-  end generate; -- /bus_request_gen
+  end generate;
 
 
   -- Response -------------------------------------------------------------------------------
@@ -535,7 +552,7 @@ begin
     variable tmp_v : bus_rsp_t;
   begin
     tmp_v := rsp_terminate_c; -- start with all-zero
-    for i in 0 to (num_devs_physical_c-1) loop -- logical OR all response signals
+    for i in 0 to (num_devs_c-1) loop -- OR all enabled response buses
       if dev_en_list_c(i) then
         tmp_v.data := tmp_v.data or dev_rsp(i).data;
         tmp_v.ack  := tmp_v.ack  or dev_rsp(i).ack;

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100006"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100007"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -700,6 +700,7 @@ package neorv32_package is
   function popcount_f(input : std_ulogic_vector) return natural;
   function leading_zeros_f(input : std_ulogic_vector) return natural;
   impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t;
+  function print_version_f(version : std_ulogic_vector(31 downto 0)) return string;
 
 -- **********************************************************************************************************
 -- NEORV32 Processor Top Entity (component prototype)
@@ -1171,6 +1172,34 @@ package body neorv32_package is
     return mem_v;
   end function mem32_init_f;
 
+  -- Print hardware version in human-readable format (xx.xx.xx.xx) --------------------------
+  -- -------------------------------------------------------------------------------------------
+  function print_version_f(version : std_ulogic_vector(31 downto 0)) return string is
+    variable res_v : string(1 to 11);
+    variable idx_v : natural;
+  begin
+    idx_v := 1;
+    if (version(31 downto 28) /= x"0") then -- print only if not trailing zero
+      res_v(idx_v) := to_hexchar_f(version(31 downto 28)); idx_v := idx_v + 1;
+    end if;
+    res_v(idx_v) := to_hexchar_f(version(27 downto 24)); idx_v := idx_v + 1;
+    res_v(idx_v) := '.'; idx_v := idx_v + 1;
+    if (version(23 downto 20) /= x"0") then -- print only if not trailing zero
+      res_v(idx_v) := to_hexchar_f(version(23 downto 20)); idx_v := idx_v + 1;
+    end if;
+    res_v(idx_v) := to_hexchar_f(version(19 downto 16)); idx_v := idx_v + 1;
+    res_v(idx_v) := '.'; idx_v := idx_v + 1;
+    if (version(15 downto 12) /= x"0") then -- print only if not trailing zero
+      res_v(idx_v) := to_hexchar_f(version(15 downto 12)); idx_v := idx_v + 1;
+    end if;
+    res_v(idx_v) := to_hexchar_f(version(11 downto 8)); idx_v := idx_v + 1;
+    res_v(idx_v) := '.'; idx_v := idx_v + 1;
+    if (version(7 downto 4) /= x"0") then -- print only if not trailing zero
+      res_v(idx_v) := to_hexchar_f(version(7 downto 4)); idx_v := idx_v + 1;
+    end if;
+    res_v(idx_v) := to_hexchar_f(version(3 downto 0)); idx_v := idx_v + 1;
+    return res_v;
+  end function print_version_f;
 
 end neorv32_package;
 

rtl/core/neorv32_sysinfo.vhd

@@ -1,5 +1,5 @@
 -- ================================================================================ --
--- NEORV32 SoC - System/Processor Configuration Information Memory (SYSINFO)        --
+-- NEORV32 SoC - System Configuration Information Memory (SYSINFO)                  --
 -- -------------------------------------------------------------------------------- --
 -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
 -- Copyright (c) NEORV32 contributors.                                              --
@@ -87,26 +87,26 @@ begin
   sysinfo(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
 
   -- SYSINFO(1): Internal Memory Configuration (sizes)
-  sysinfo(1)(07 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size)
-  sysinfo(1)(15 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size)
+  sysinfo(1)(7  downto 0)  <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size)
+  sysinfo(1)(15 downto 8)  <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size)
   sysinfo(1)(23 downto 16) <= (others => '0'); -- reserved
   sysinfo(1)(31 downto 24) <= std_ulogic_vector(to_unsigned(index_size_f(AMO_RVS_GRANULARITY), 8)); -- log2(reservation set granularity)
 
   -- SYSINFO(2): SoC Configuration --
-  sysinfo(2)(00) <= '1' when INT_BOOTLOADER_EN   else '0'; -- processor-internal bootloader implemented?
-  sysinfo(2)(01) <= '1' when XBUS_EN             else '0'; -- external bus interface implemented?
-  sysinfo(2)(02) <= '1' when int_imem_en_c       else '0'; -- processor-internal instruction memory implemented?
-  sysinfo(2)(03) <= '1' when int_dmem_en_c       else '0'; -- processor-internal data memory implemented?
-  sysinfo(2)(04) <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented?
-  sysinfo(2)(05) <= '1' when ICACHE_EN           else '0'; -- processor-internal instruction cache implemented?
-  sysinfo(2)(06) <= '1' when DCACHE_EN           else '0'; -- processor-internal data cache implemented?
-  sysinfo(2)(07) <= '1' when CLOCK_GATING_EN     else '0'; -- enable clock gating when in sleep mode
-  sysinfo(2)(08) <= '1' when xcache_en_c         else '0'; -- external bus interface cache implemented?
-  sysinfo(2)(09) <= '1' when XIP_EN              else '0'; -- execute in place module implemented?
+  sysinfo(2)(0)  <= '1' when INT_BOOTLOADER_EN   else '0'; -- processor-internal bootloader implemented?
+  sysinfo(2)(1)  <= '1' when XBUS_EN             else '0'; -- external bus interface implemented?
+  sysinfo(2)(2)  <= '1' when int_imem_en_c       else '0'; -- processor-internal instruction memory implemented?
+  sysinfo(2)(3)  <= '1' when int_dmem_en_c       else '0'; -- processor-internal data memory implemented?
+  sysinfo(2)(4)  <= '1' when ON_CHIP_DEBUGGER_EN else '0'; -- on-chip debugger implemented?
+  sysinfo(2)(5)  <= '1' when ICACHE_EN           else '0'; -- processor-internal instruction cache implemented?
+  sysinfo(2)(6)  <= '1' when DCACHE_EN           else '0'; -- processor-internal data cache implemented?
+  sysinfo(2)(7)  <= '1' when CLOCK_GATING_EN     else '0'; -- enable clock gating when in sleep mode
+  sysinfo(2)(8)  <= '1' when xcache_en_c         else '0'; -- external bus interface cache implemented?
+  sysinfo(2)(9)  <= '1' when XIP_EN              else '0'; -- execute in place module implemented?
   sysinfo(2)(10) <= '1' when xip_cache_en_c      else '0'; -- execute in place cache implemented?
-  sysinfo(2)(11) <= '0'; -- reserved
-  sysinfo(2)(12) <= '0'; -- reserved
-  sysinfo(2)(13) <= '0'; -- reserved
+  sysinfo(2)(11) <= '0';                                   -- reserved
+  sysinfo(2)(12) <= '0';                                   -- reserved
+  sysinfo(2)(13) <= '0';                                   -- reserved
   sysinfo(2)(14) <= '1' when IO_DMA_EN           else '0'; -- direct memory access controller (DMA) implemented?
   sysinfo(2)(15) <= '1' when IO_GPIO_EN          else '0'; -- general purpose input/output port unit (GPIO) implemented?
   sysinfo(2)(16) <= '1' when IO_MTIME_EN         else '0'; -- machine system timer (MTIME) implemented?
@@ -127,10 +127,10 @@ begin
   sysinfo(2)(31) <= '1' when IO_CRC_EN           else '0'; -- cyclic redundancy check unit (CRC) implemented?
 
   -- SYSINFO(3): Cache Configuration --
-  sysinfo(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(block_size_in_bytes)
-  sysinfo(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(number_of_block)
+  sysinfo(3)(3 downto 0)   <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(block_size_in_bytes)
+  sysinfo(3)(7 downto 4)   <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when ICACHE_EN else (others => '0'); -- i-cache: log2(number_of_block)
   --
-  sysinfo(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_BLOCK_SIZE), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(block_size)
+  sysinfo(3)(11 downto 8)  <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_BLOCK_SIZE), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(block_size)
   sysinfo(3)(15 downto 12) <= std_ulogic_vector(to_unsigned(index_size_f(DCACHE_NUM_BLOCKS), 4)) when DCACHE_EN else (others => '0'); -- d-cache: log2(num_blocks)
   --
   sysinfo(3)(19 downto 16) <= std_ulogic_vector(to_unsigned(index_size_f(XIP_CACHE_BLOCK_SIZE), 4)) when xip_cache_en_c else (others => '0'); -- xip-cache: log2(block_size_in_bytes)