minor rtl fixes

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 24.04.2024 | 1.9.8.7 | minor RTL fixes | [#883](https://github.com/stnolting/neorv32/pull/883) |
 | 23.04.2024 | 1.9.8.6 | :bug: fix on-chip-debugger external-halt-request vs. exception concurrency | [#882](https://github.com/stnolting/neorv32/pull/882) |
 | 21.04.2024 | 1.9.8.5 | rtl cleanups and (area) optimizations | [#880](https://github.com/stnolting/neorv32/pull/880) |
 | 16.04.2024 | 1.9.8.4 | :warning: use a 4-bit FIRQ select instead of a 16-bit FIRQ mask for DMA auto-trigger configuration | [#877](https://github.com/stnolting/neorv32/pull/877) |

rtl/core/neorv32_cpu_cp_cond.vhd

@@ -37,7 +37,8 @@ architecture neorv32_cpu_cp_cond_rtl of neorv32_cpu_cp_cond is
 
 begin
 
-  -- conditional output --
+  -- Conditional Output ---------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
   cond_out: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then

rtl/core/neorv32_cpu_cp_fpu.vhd

@@ -1153,7 +1153,7 @@ begin
               addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
             end if;
           else
-            --  roundTowardNegative; under that attribute, the sign of an exact zero sum (or difference) shall be −0
+            --  roundTowardNegative; under that attribute, the sign of an exact zero sum (or difference) shall be -0
             if (fpu_operands.frm = "010") then -- round down (towards -infinity)
               addsub.res_sign <= '1'; -- set the sign to 0 to generate a +0.0 result
             else
@@ -1172,7 +1172,7 @@ begin
               addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
             end if;
           else
-            --  roundTowardNegative; under that attribute, the sign of an exact zero sum (or difference) shall be −0
+            --  roundTowardNegative; under that attribute, the sign of an exact zero sum (or difference) shall be -0
             if (fpu_operands.frm = "010") then -- round down (towards -infinity)
               addsub.res_sign <= '1'; -- set the sign to 0 to generate a +0.0 result
             else

rtl/core/neorv32_cpu_pmp.vhd

@@ -293,8 +293,10 @@ begin
 
     -- check region match according to configured mode --
     match_gen: process(csr, region)
+      variable tmp_v : std_ulogic_vector(1 downto 0);
     begin
-      case csr.cfg(r)(cfg_ah_c downto cfg_al_c) is
+      tmp_v := csr.cfg(r)(cfg_ah_c downto cfg_al_c);
+      case tmp_v is -- VHDL/GHDL issue: "object type is not locally static"
         when mode_off_c => -- entry disabled
           region.i_match(r) <= '0';
           region.d_match(r) <= '0';

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090806"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090807"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

rtl/core/neorv32_uart.vhd

@@ -18,7 +18,7 @@ use std.textio.all;
 
 entity neorv32_uart is
   generic (
-    SIM_LOG_FILE : string;  -- name of SIM mode log file
+    SIM_LOG_FILE : string; -- name of SIM mode log file
     UART_RX_FIFO : natural range 1 to 2**15; -- RX fifo depth, has to be a power of two, min 1
     UART_TX_FIFO : natural range 1 to 2**15  -- TX fifo depth, has to be a power of two, min 1
   );
@@ -115,7 +115,7 @@ architecture neorv32_uart_rtl of neorv32_uart is
   -- UART receiver --
   type rx_engine_t is record
     state   : std_ulogic_vector(1 downto 0);
-    sreg    : std_ulogic_vector(9 downto 0);
+    sreg    : std_ulogic_vector(8 downto 0);
     bitcnt  : std_ulogic_vector(3 downto 0);
     baudcnt : std_ulogic_vector(9 downto 0);
     done    : std_ulogic;
@@ -337,9 +337,10 @@ begin
             tx_engine.state(1 downto 0) <= "01";
           end if;
 
-        when "101" => -- WAIT: check if we are allowed to start sending
+        when "101" => -- WAIT: check if we can start sending
         -- ------------------------------------------------------------
-          if (tx_engine.cts_sync(1) = '0') or (ctrl.hwfc_en = '0') then -- allowed to send OR flow-control disabled
+          if (uart_clk = '1') and -- start with next clock tick
+             ((tx_engine.cts_sync(1) = '0') or (ctrl.hwfc_en = '0')) then -- allowed to send OR flow-control disabled
             tx_engine.state(1 downto 0) <= "11";
           end if;
 
@@ -390,8 +391,7 @@ begin
       -- input synchronizer --
       rx_engine.sync(2) <= uart_rxd_i;
       if (uart_clk = '1') then
-        rx_engine.sync(1) <= rx_engine.sync(2);
-        rx_engine.sync(0) <= rx_engine.sync(1);
+        rx_engine.sync(1 downto 0) <= rx_engine.sync(2 downto 1);
       end if;
 
       -- defaults --