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[fifo] fix (Vivado) synthesis issue #827

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Feb 23, 2024
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[fifo] fix (Vivado) synthesis issue #827

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dda3248
[fifo] fix (Vivado) synthesis issue
stnolting Feb 23, 2024
9afb054
[fifos] use all provided generics
stnolting Feb 23, 2024
8c27aae
[changelog] add v1.9.5.7
stnolting Feb 23, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Link |
|:----:|:-------:|:--------|:----:|
| 23.02.2024 | 1.9.5.7 | fix FIFO synthesis issue (Vivado cannot infer block RAM nor LUT-RAM) | [#827](https://github.com/stnolting/neorv32/pull/827) |
| 20.02.2024 | 1.9.5.6 | :bug: fix bug in `mip.firq` CSR access; `mip.firq` bits are now read-write - software can trigger FIRQs by writing `1` to the according CSR bit | [#821](https://github.com/stnolting/neorv32/pull/821) |
| 19.02.2024 | 1.9.5.5 | SLINK: add native hardware support for AXI-stream's "tlast" signal | [#815](https://github.com/stnolting/neorv32/pull/815) |
| 19.02.2024 | 1.9.5.4 | :warning: remove support of `Smcntrpmf` ISA extension (counter privilege mode filtering) | [#814](https://github.com/stnolting/neorv32/pull/814) |
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3 changes: 2 additions & 1 deletion rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -433,7 +433,8 @@ begin
FIFO_DEPTH => 2, -- number of fifo entries; has to be a power of two, min 2
FIFO_WIDTH => ipb.wdata(i)'length, -- size of data elements in fifo
FIFO_RSYNC => false, -- we NEED to read data asynchronously
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external logic)
FIFO_SAFE => false, -- no safe access required (ensured by FIFO-external logic)
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
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31 changes: 17 additions & 14 deletions rtl/core/neorv32_fifo.vhd
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Expand Up @@ -70,7 +70,8 @@ architecture neorv32_fifo_rtl of neorv32_fifo is

-- FIFO storage --
type fifo_mem_t is array (0 to fifo_depth_c-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_mem : fifo_mem_t;
signal fifo_mem : fifo_mem_t; -- for fifo_depth_c > 1
signal fifo_reg : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- for fifo_depth_c = 1

-- FIFO control --
signal we, re : std_ulogic; -- write-/read-enable
Expand Down Expand Up @@ -113,6 +114,7 @@ begin
end if;
end process pointer_update;

-- more than 1 FIFO entries --
check_large:
if (fifo_depth_c > 1) generate
match <= '1' when (r_pnt(r_pnt'left-1 downto 0) = w_pnt(w_pnt'left-1 downto 0)) else '0';
Expand All @@ -122,6 +124,7 @@ begin
half <= diff(diff'left-1) or full;
end generate;

-- just 1 FIFO entry --
check_small:
if (fifo_depth_c = 1) generate
match <= '1' when (r_pnt(0) = w_pnt(0)) else '0';
Expand All @@ -138,20 +141,21 @@ begin
-- -------------------------------------------------------------------------------------------
memory_full_reset: -- cannot be mapped to block RAM!
if FULL_RESET generate
fifo_write: process(rstn_i, clk_i)
fifo_write_rst: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
fifo_mem <= (others => (others => '0')); -- full reset of memory cells
fifo_mem <= (others => (others => '0'));
fifo_reg <= (others => '0');
elsif rising_edge(clk_i) then
if (we = '1') then
if (fifo_depth_c > 1) then -- prevent a NULL assertion for fifo_depth_c of 1
if (fifo_depth_c > 1) then
fifo_mem(to_integer(unsigned(w_pnt(w_pnt'left-1 downto 0)))) <= wdata_i;
else
fifo_mem(0) <= wdata_i;
fifo_reg <= wdata_i;
end if;
end if;
end if;
end process fifo_write;
end process fifo_write_rst;
end generate;

memory_no_reset: -- no reset to infer block RAM
Expand All @@ -160,10 +164,10 @@ begin
begin
if rising_edge(clk_i) then
if (we = '1') then
if (fifo_depth_c > 1) then-- prevent a NULL assertion for fifo_depth_c of 1
if (fifo_depth_c > 1) then
fifo_mem(to_integer(unsigned(w_pnt(w_pnt'left-1 downto 0)))) <= wdata_i;
else
fifo_mem(0) <= wdata_i;
fifo_reg <= wdata_i;
end if;
end if;
end if;
Expand All @@ -175,8 +179,7 @@ begin
-- -------------------------------------------------------------------------------------------
fifo_read_async: -- asynchronous read
if not FIFO_RSYNC generate
-- prevent a NULL assertion for fifo_depth_c of 1 --
rdata_o <= fifo_mem(to_integer(unsigned(r_pnt(r_pnt'left-1 downto 0)))) when (fifo_depth_c > 1) else fifo_mem(0);
rdata_o <= fifo_mem(to_integer(unsigned(r_pnt(r_pnt'left-1 downto 0)))) when (fifo_depth_c > 1) else fifo_reg;
-- status --
free_o <= free;
avail_o <= avail;
Expand All @@ -188,15 +191,15 @@ begin
sync_read: process(clk_i)
begin
if rising_edge(clk_i) then
if (fifo_depth_c > 1) then -- prevent a NULL assertion for fifo_depth_c of 1
if (fifo_depth_c > 1) then
rdata_o <= fifo_mem(to_integer(unsigned(r_pnt(r_pnt'left-1 downto 0))));
else
rdata_o <= fifo_mem(0);
rdata_o <= fifo_reg;
end if;
end if;
end process sync_read;
-- status --
sync_status_flags: process(rstn_i, clk_i)
sync_status: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
free_o <= '0';
Expand All @@ -207,7 +210,7 @@ begin
avail_o <= avail;
half_o <= half;
end if;
end process sync_status_flags;
end process sync_status;
end generate;


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3 changes: 2 additions & 1 deletion rtl/core/neorv32_neoled.vhd
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Expand Up @@ -225,7 +225,8 @@ begin
FIFO_DEPTH => FIFO_DEPTH, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 32+2, -- size of data elements in fifo
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_package.vhd
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Expand Up @@ -53,7 +53,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090506"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090507"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

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3 changes: 2 additions & 1 deletion rtl/core/neorv32_sdi.vhd
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Expand Up @@ -202,7 +202,8 @@ begin
FIFO_DEPTH => RTX_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 8, -- size of data elements in fifo (32-bit only for simulation)
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
Expand Down
6 changes: 4 additions & 2 deletions rtl/core/neorv32_slink.vhd
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Expand Up @@ -217,7 +217,8 @@ begin
FIFO_DEPTH => SLINK_RX_FIFO,
FIFO_WIDTH => 32+1, -- data + last-flag
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
Expand Down Expand Up @@ -265,7 +266,8 @@ begin
FIFO_DEPTH => SLINK_TX_FIFO,
FIFO_WIDTH => 32+1, -- data + last-flag
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
Expand Down
6 changes: 4 additions & 2 deletions rtl/core/neorv32_spi.vhd
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Expand Up @@ -234,7 +234,8 @@ begin
FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 8, -- size of data elements in fifo
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
Expand Down Expand Up @@ -264,7 +265,8 @@ begin
FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 8, -- size of data elements in fifo
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
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3 changes: 2 additions & 1 deletion rtl/core/neorv32_trng.vhd
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Expand Up @@ -195,7 +195,8 @@ begin
FIFO_DEPTH => IO_TRNG_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 8, -- size of data elements in fifo
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => true -- safe access
FIFO_SAFE => true, -- safe access
FULL_RESET => false -- no HW reset, try to infer BRAM
)
port map (
-- control --
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6 changes: 4 additions & 2 deletions rtl/core/neorv32_uart.vhd
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Expand Up @@ -267,7 +267,8 @@ begin
FIFO_DEPTH => UART_TX_FIFO,
FIFO_WIDTH => 8,
FIFO_RSYNC => true,
FIFO_SAFE => true
FIFO_SAFE => true,
FULL_RESET => false
)
port map (
-- control --
Expand Down Expand Up @@ -308,7 +309,8 @@ begin
FIFO_DEPTH => UART_RX_FIFO,
FIFO_WIDTH => 8,
FIFO_RSYNC => true,
FIFO_SAFE => true
FIFO_SAFE => true,
FULL_RESET => false
)
port map (
clk_i => clk_i,
Expand Down