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🐛 fix fence signal pass-through in caches #802

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merged 2 commits into from
Feb 10, 2024
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🐛 fix fence signal pass-through in caches #802

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72044a0
:bug: fix fence signal pass-through in caches
stnolting Feb 10, 2024
e55dbad
[changelog] add v1.9.4.8
stnolting Feb 10, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Link |
|:----:|:-------:|:--------|:----:|
| 10.02.2024 | 1.9.4.8 | :bug: fix missing fence pass-through in caches | [#802](https://github.com/stnolting/neorv32/pull/802) |
| 09.02.2024 | 1.9.4.7 | :warning: integrate fence signal into CPU bus, remove top entity's fence signals | (#800)[https://github.com/stnolting/neorv32/pull/800] |
| 09.02.2024 | 1.9.4.6 | :sparkles: add configurable XIP cache | [#799](https://github.com/stnolting/neorv32/pull/799) |
| 09.02.2024 | 1.9.4.5 | :bug: close further illegal compressed instruction encoding loopholes | [#797](https://github.com/stnolting/neorv32/pull/797) |
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1 change: 1 addition & 0 deletions rtl/core/neorv32_dcache.vhd
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Expand Up @@ -187,6 +187,7 @@ begin
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.stb <= '0';
bus_req_o.fence <= cpu_req_i.fence;

-- fsm --
case ctrl.state is
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1 change: 1 addition & 0 deletions rtl/core/neorv32_icache.vhd
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Expand Up @@ -189,6 +189,7 @@ begin
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.fence <= cpu_req_i.fence;

-- fsm --
case ctrl.state is
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_package.vhd
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Expand Up @@ -56,7 +56,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090407"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090408"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

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31 changes: 16 additions & 15 deletions rtl/core/neorv32_xip.vhd
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Expand Up @@ -808,27 +808,28 @@ begin
ctrl_engine_fsm_comb: process(state, addr_reg, cache, clear_i, cpu_req_i, bus_rsp_i)
begin
-- control defaults --
state_nxt <= state;
addr_reg_nxt <= addr_reg;
state_nxt <= state;
addr_reg_nxt <= addr_reg;

-- cache defaults --
cache.ctrl_en <= '0';
cache.ctrl_we <= '0';
cache.ctrl_en <= '0';
cache.ctrl_we <= '0';

-- host response defaults --
cpu_rsp_o.ack <= '0';
cpu_rsp_o.err <= '0';
cpu_rsp_o.data <= (others => '0');
cpu_rsp_o.ack <= '0';
cpu_rsp_o.err <= '0';
cpu_rsp_o.data <= (others => '0');

-- bus interface defaults --
bus_req_o.data <= (others => '0');
bus_req_o.ben <= (others => '0');
bus_req_o.src <= cpu_req_i.src;
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.addr <= addr_reg;
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.data <= (others => '0');
bus_req_o.ben <= (others => '0');
bus_req_o.src <= cpu_req_i.src;
bus_req_o.priv <= cpu_req_i.priv;
bus_req_o.addr <= addr_reg;
bus_req_o.rw <= '0'; -- read-only
bus_req_o.stb <= '0';
bus_req_o.rvso <= cpu_req_i.rvso;
bus_req_o.fence <= cpu_req_i.fence;

-- fsm --
case state is
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