clk_i: main clock, can be switched off
clk_aux_i: always-on clock

- SYSINFO->SOC bit 7
- some minor VHDL clean-ups (remove use of custom bool-to-std_ulogic function)

- minor code clean-ups (remove private print true/false function)

default = false; update version ID

- add new CLOCK_GATING_EN generic

- simplify instruction fetch engine: remove PARKED state, use the IPB FIFO level to check if the instruction fetch has halted
- make sure halt request signal is not registered by the switched-off clock
- add registered sleep mode signal

- add CPU's clk_aux_i port
- add new processor generic CLOCK_GATING_EN
- refine section "sleep mode"