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[rtl] minor code cleanups #760

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Jan 8, 2024
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[rtl] minor code cleanups #760

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1e2fa55
[rtl] minor code cleanups
stnolting Jan 8, 2024
071e1d6
[CHANGELOG] add version 1.9.2.9
stnolting Jan 8, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Link |
|:----:|:-------:|:--------|:----:|
| 08.01.2024 | 1.9.2.9 | minor rtl code cleanups | [#760](https://github.com/stnolting/neorv32/pull/760) |
| 06.01.2024 | 1.9.2.8 | :sparkles: add timer-capture mode to General Purpose Timer (GPTMR); :warning: remove "single-shot" mode, change control register layout | [#759](https://github.com/stnolting/neorv32/pull/759) |
| 19.12.2023 | 1.9.2.7 | minor rtl code cleanups, edits and optimization; :lock: reset `mtvec`, `mepc` and `dpc` CSRs to CPU boot address (`CPU_BOOT_ADDR` CPU generic) | [#755](https://github.com/stnolting/neorv32/pull/755) |
| 19.12.2023 | 1.9.2.6 | rework FIFO component fixing problems with inferring block RAM | [#754](https://github.com/stnolting/neorv32/pull/754) |
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4 changes: 2 additions & 2 deletions rtl/core/neorv32_cpu.vhd
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Expand Up @@ -3,7 +3,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -298,7 +298,7 @@ begin
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
-- Tuning Options --
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
)
port map (
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8 changes: 4 additions & 4 deletions rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -969,7 +969,7 @@ begin
end if;

-- load upper immediate / add upper immediate to PC --
when opcode_lui_c | opcode_auipc_c =>
when opcode_lui_c | opcode_auipc_c =>
if (execute_engine.ir(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
ctrl_nxt.alu_op <= alu_op_movb_c; -- pass immediate
else -- AUIPC
Expand All @@ -991,17 +991,17 @@ begin
execute_engine.state_nxt <= FENCE;

-- FPU: floating-point operations --
when opcode_fop_c =>
when opcode_fop_c =>
ctrl_nxt.alu_cp_trig(cp_sel_fpu_c) <= '1'; -- trigger FPU CP
execute_engine.state_nxt <= ALU_WAIT; -- will be aborted via monitor exception if FPU not implemented

-- CFU: custom RISC-V instructions --
when opcode_cust0_c | opcode_cust1_c | opcode_cust2_c | opcode_cust3_c =>
when opcode_cust0_c | opcode_cust1_c | opcode_cust2_c | opcode_cust3_c =>
ctrl_nxt.alu_cp_trig(cp_sel_cfu_c) <= '1'; -- trigger CFU CP
execute_engine.state_nxt <= ALU_WAIT; -- will be aborted via monitor exception if CFU not implemented

-- environment/CSR operation or ILLEGAL opcode --
when others =>
when others =>
csr.re_nxt <= '1';
execute_engine.state_nxt <= SYSTEM;

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20 changes: 11 additions & 9 deletions rtl/core/neorv32_cpu_cp_shifter.vhd
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Expand Up @@ -6,7 +6,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -44,7 +44,7 @@ use neorv32.neorv32_package.all;

entity neorv32_cpu_cp_shifter is
generic (
FAST_SHIFT_EN : boolean -- implement fast but large barrel shifter
FAST_SHIFT_EN : boolean -- implement fast but large barrel shifter
);
port (
-- global control --
Expand Down Expand Up @@ -86,7 +86,7 @@ begin
serial_shifter:
if not FAST_SHIFT_EN generate

serial_shifter_core: process(rstn_i, clk_i)
serial_shifter: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
shifter.busy <= '0';
Expand Down Expand Up @@ -114,7 +114,7 @@ begin
end if;
end if;
end if;
end process serial_shifter_core;
end process serial_shifter;

-- shift control/output --
shifter.done <= '1' when (or_reduce_f(shifter.cnt(shifter.cnt'left downto 1)) = '0') else '0';
Expand All @@ -130,9 +130,9 @@ begin
if FAST_SHIFT_EN generate

-- shifter core --
barrel_shifter_core: process(rs1_i, shamt_i, ctrl_i, bs_level)
barrel_shifter: process(rs1_i, shamt_i, ctrl_i, bs_level)
begin
-- input layer: convert left shifts to right shifts by reversing --
-- input layer: convert left shifts to right shifts by bit-reversal --
if (ctrl_i.ir_funct3(2) = '0') then -- is left shift?
bs_level(index_size_f(XLEN)) <= bit_rev_f(rs1_i); -- reverse bit order of input operand
else
Expand All @@ -141,13 +141,13 @@ begin
-- shifter array (right-shifts only) --
for i in (index_size_f(XLEN)-1) downto 0 loop
if (shamt_i(i) = '1') then
bs_level(i)(XLEN-1 downto XLEN-(2**i)) <= (others => (bs_level(i+1)(XLEN-1) and ctrl_i.ir_funct12(10)));
bs_level(i)(XLEN-1 downto XLEN-(2**i)) <= (others => (bs_level(i+1)(XLEN-1) and ctrl_i.ir_funct12(10))); -- arithmetic/logical
bs_level(i)((XLEN-(2**i))-1 downto 0) <= bs_level(i+1)(XLEN-1 downto 2**i);
else
bs_level(i) <= bs_level(i+1);
end if;
end loop;
end process barrel_shifter_core;
end process barrel_shifter;

-- pipeline register --
barrel_shifter_buf: process(rstn_i, clk_i)
Expand All @@ -162,7 +162,9 @@ begin
end process barrel_shifter_buf;

-- output layer: output gate and re-convert original left shifts --
res_o <= (others => '0') when (bs_start = '0') else bit_rev_f(bs_result) when (ctrl_i.ir_funct3(2) = '0') else bs_result;
res_o <= (others => '0') when (bs_start = '0') else
bit_rev_f(bs_result) when (ctrl_i.ir_funct3(2) = '0') else
bs_result;

-- processing done --
valid_o <= start_i;
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10 changes: 5 additions & 5 deletions rtl/core/neorv32_cpu_pmp.vhd
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Expand Up @@ -3,7 +3,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -244,10 +244,10 @@ begin
end generate;

-- pack configuration read-back --
cfg_rd32(0) <= cfg_rd(03) & cfg_rd(02) & cfg_rd(01) & cfg_rd(00);
cfg_rd32(1) <= cfg_rd(07) & cfg_rd(06) & cfg_rd(05) & cfg_rd(04);
cfg_rd32(2) <= cfg_rd(11) & cfg_rd(10) & cfg_rd(09) & cfg_rd(08);
cfg_rd32(3) <= cfg_rd(15) & cfg_rd(14) & cfg_rd(13) & cfg_rd(12);
csr_read_back_pack:
for i in 0 to 3 generate
cfg_rd32(i) <= cfg_rd(i*4+3) & cfg_rd(i*4+2) & cfg_rd(i*4+1) & cfg_rd(i*4+0);
end generate;


-- Region Access Logic --------------------------------------------------------------------
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19 changes: 7 additions & 12 deletions rtl/core/neorv32_debug_dtm.vhd
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Expand Up @@ -2,11 +2,11 @@
-- # << NEORV32 - RISC-V Debug Transport Module (DTM) >> #
-- # ********************************************************************************************* #
-- # Provides a JTAG-compatible TAP to access the DMI register interface. #
-- # Compatible to the RISC-V debug specification version 1.0. #
-- # Compatible to the RISC-V debug specification version 0.13 and 1.0. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2024, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -298,7 +298,6 @@ begin
dmi_ctrl.wdata <= (others => '0');
dmi_ctrl.addr <= (others => '0');
elsif rising_edge(clk_i) then

-- DMI reset control --
if (dr_trigger.valid = '1') and (tap_reg.ireg = addr_dtmcs_c) then
dmi_ctrl.dmireset <= tap_reg.dtmcs(16);
Expand All @@ -318,7 +317,6 @@ begin
-- DMI interface arbiter --
dmi_ctrl.op <= dmi_req_nop_c; -- default
if (dmi_ctrl.busy = '0') then -- idle: waiting for new request

if (dmi_ctrl.dmihardreset = '0') then -- no DMI hard reset
if (dr_trigger.valid = '1') and (tap_reg.ireg = addr_dmi_c) then
dmi_ctrl.addr <= tap_reg.dmi(40 downto 34);
Expand All @@ -329,14 +327,11 @@ begin
end if;
end if;
end if;

else -- busy: read/write access in progress

dmi_ctrl.rdata <= dmi_rsp_i.data;
if (dmi_rsp_i.ack = '1') then
dmi_ctrl.busy <= '0';
end if;

else -- busy: read/write access in progress
dmi_ctrl.rdata <= dmi_rsp_i.data;
if (dmi_rsp_i.ack = '1') then
dmi_ctrl.busy <= '0';
end if;
end if;
end if;
end process dmi_controller;
Expand Down
2 changes: 1 addition & 1 deletion rtl/core/neorv32_package.vhd
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Expand Up @@ -56,7 +56,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090208"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090209"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

Expand Down