stnolting · stnolting · Dec 20, 2023 · Dec 19, 2023 · Dec 19, 2023 · Dec 19, 2023
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Link |
 |:----:|:-------:|:--------|:----:|
+| 19.12.2023 | 1.9.2.7 | minor rtl code cleanups, edits and optimization; :lock: reset `mtvec`, `mepc` and `dpc` CSRs to CPU boot address (`CPU_BOOT_ADDR` CPU generic) | [#755](https://github.com/stnolting/neorv32/pull/755) |
 | 19.12.2023 | 1.9.2.6 | rework FIFO component fixing problems with inferring block RAM | [#754](https://github.com/stnolting/neorv32/pull/754) |
 | 11.12.2023 | 1.9.2.5 | clean-up software framework | [#752](https://github.com/stnolting/neorv32/pull/752) |
 | 09.12.2023 | 1.9.2.4 | minor rtl code cleanups | [#747](https://github.com/stnolting/neorv32/pull/747) |
@@ -136,7 +137,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 | 17.03.2023 | 1.8.2.4 | re-add VHDL process names | [#555](https://github.com/stnolting/neorv32/pull/555) |
 | 15.03.2023 | 1.8.2.3 | rtl reworks, cleanups and optimizations | [#550](https://github.com/stnolting/neorv32/pull/550) |
 | 11.03.2023 | 1.8.2.2 | :sparkles: add support for RISC-V `Zicond` ISA extension (conditional operations) | [#546](https://github.com/stnolting/neorv32/pull/546) |
-| 10.02.2023 | 1.8.2.1 | rtl code edits, clean-ups and minor optimizations (improve branch prediction) | [#545](https://github.com/stnolting/neorv32/pull/545) |
+| 10.03.2023 | 1.8.2.1 | rtl code edits, clean-ups and minor optimizations (improve branch prediction) | [#545](https://github.com/stnolting/neorv32/pull/545) |
 | 10.03.2023 | [**:rocket:1.8.2**](https://github.com/stnolting/neorv32/releases/tag/v1.8.2) | **New release** | |
 | 09.03.2023 | 1.8.1.10 | :warning: move tri-state drivers (ONEWIRE and TWI) out of the core | [#543](https://github.com/stnolting/neorv32/pull/543) |
 | 08.03.2023 | 1.8.1.9 | reintegrate **UART** RTS/CTS hardware flow-control | [#541](https://github.com/stnolting/neorv32/pull/541) |

diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc
@@ -276,7 +276,7 @@ Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr`
 |=======================
 | Name        | Machine trap-handler base address
 | Address     | `0x305`
-| Reset value | `0x00000000`
+| Reset value | `CPU_BOOT_ADDR`, CPU boot address, 4-byte aligned (see <<_cpu_top_entity_generics>> and <<_address_space>>)
 | ISA         | `Zicsr`
 | Description | The `mtvec` CSR holds the trap vector configuration.
 |=======================
@@ -368,7 +368,7 @@ or entirely denied allowing access to **none** counter CSRs.
 |=======================
 | Name        | Machine exception program counter
 | Address     | `0x341`
-| Reset value | `0x00000000`
+| Reset value | `CPU_BOOT_ADDR`, CPU boot address, 4-byte aligned (see <<_cpu_top_entity_generics>> and <<_address_space>>)
 | ISA         | `Zicsr`
 | Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when
 an instruction is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values.

diff --git a/docs/datasheet/on_chip_debugger.adoc b/docs/datasheet/on_chip_debugger.adoc
@@ -628,7 +628,7 @@ Cause codes in `dcsr.cause` (highest priority first):
 |=======================
 | Name        | Debug program counter
 | Address     | `0x7b1`
-| Reset value | `0x00000000`
+| Reset value | `CPU_BOOT_ADDR`, CPU boot address, 4-byte aligned (see <<_cpu_top_entity_generics>> and <<_address_space>>)
 | ISA         | `Zicsr` & `Sdext`
 | Description | The register is used to store the current program counter when debug mode is entered. The `dret` instruction will
 return to the address stored in `dpc` by automatically moving `dpc` to the program counter.

diff --git a/docs/datasheet/soc_uart.adoc b/docs/datasheet/soc_uart.adoc
@@ -56,7 +56,7 @@ Disabling the module via the `UART_CTRL_EN` bit will also clear these FIFOs.
 A new TX transmission is started by writing to the `DATA` register. The
 transfer is completed when the `UART_CTRL_TX_BUSY` control register flag returns to zero. RX data is available when
 the `UART_CTRL_RX_NEMPTY` flag becomes set. The `UART_CTRL_RX_OVER` will be set if the RX FIFO overflows. This flag
-is cleared by reading the `DATA` register or by disabling the module.
+is cleared only by disabling the module via `UART_CTRL_EN`.
 
 
 **UART Interrupts**
@@ -136,7 +136,7 @@ Both file are created in the simulation's home folder.
                                   <|`25`    `UART_CTRL_IRQ_TX_EMPTY`            ^| r/w <| fire IRQ if TX FIFO empty
                                   <|`26`    `UART_CTRL_IRQ_TX_NHALF`            ^| r/w <| fire IRQ if TX not at least half full
                                   <|`29:27` -                                   ^| r/- <| _reserved_ read as zero
-                                  <|`30`    `UART_CTRL_RX_OVER`                 ^| r/- <| RX FIFO overflow
+                                  <|`30`    `UART_CTRL_RX_OVER`                 ^| r/- <| RX FIFO overflow; cleared by disabling the module
                                   <|`31`    `UART_CTRL_TX_BUSY`                 ^| r/- <| TX busy or TX FIFO not empty
 .4+<| `0xfffff504` .4+<| `DATA` <|`7:0`   `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB`                   ^| r/w <| receive/transmit data
                                 <|`11:8`  `UART_DATA_RX_FIFO_SIZE_MSB : UART_DATA_RX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size)

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -919,8 +919,8 @@ begin
       -- ------------------------------------------------------------
         case decode_aux.opcode is
 
-          when opcode_alu_c | opcode_alui_c => -- register/immediate ALU operation
-          -- ------------------------------------------------------------
+          -- register/immediate ALU operation --
+          when opcode_alu_c | opcode_alui_c =>
             -- ALU core operation --
             case execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU operation (re-coding)
               when funct3_subadd_c => -- ADD(I), SUB
@@ -968,8 +968,8 @@ begin
               execute_engine.state_nxt <= DISPATCH;
             end if;
 
-          when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
-          -- ------------------------------------------------------------
+          -- load upper immediate / add upper immediate to PC --
+          when opcode_lui_c | opcode_auipc_c => 
             if (execute_engine.ir(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
               ctrl_nxt.alu_op <= alu_op_movb_c; -- pass immediate
             else -- AUIPC
@@ -978,30 +978,30 @@ begin
             ctrl_nxt.rf_wb_en        <= '1'; -- valid RF write-back
             execute_engine.state_nxt <= DISPATCH;
 
-          when opcode_load_c | opcode_store_c | opcode_amo_c => -- memory access
-          -- ------------------------------------------------------------
+          -- memory access --
+          when opcode_load_c | opcode_store_c | opcode_amo_c =>
             execute_engine.state_nxt <= MEM_REQ;
 
-          when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link / with register
-          -- ------------------------------------------------------------
+          -- branch / jump and link / with register --
+          when opcode_branch_c | opcode_jal_c | opcode_jalr_c =>
             execute_engine.state_nxt <= BRANCH;
 
-          when opcode_fence_c => -- memory fence operations
-          -- ------------------------------------------------------------
+          -- memory fence operations --
+          when opcode_fence_c =>
             execute_engine.state_nxt <= FENCE;
 
-          when opcode_fop_c => -- FPU: floating-point operations
-          -- ------------------------------------------------------------
+          -- FPU: floating-point operations --
+          when opcode_fop_c => 
             ctrl_nxt.alu_cp_trig(cp_sel_fpu_c) <= '1'; -- trigger FPU CP
             execute_engine.state_nxt           <= ALU_WAIT; -- will be aborted via monitor exception if FPU not implemented
 
-          when opcode_cust0_c | opcode_cust1_c | opcode_cust2_c | opcode_cust3_c => -- CFU: custom RISC-V instructions
-          -- ------------------------------------------------------------
+          -- CFU: custom RISC-V instructions --
+          when opcode_cust0_c | opcode_cust1_c | opcode_cust2_c | opcode_cust3_c => 
             ctrl_nxt.alu_cp_trig(cp_sel_cfu_c) <= '1'; -- trigger CFU CP
             execute_engine.state_nxt           <= ALU_WAIT; -- will be aborted via monitor exception if CFU not implemented
 
-          when others => -- environment/CSR operation or ILLEGAL opcode
-          -- ------------------------------------------------------------
+          -- environment/CSR operation or ILLEGAL opcode --
+          when others => 
             csr.re_nxt               <= '1';
             execute_engine.state_nxt <= SYSTEM;
 
@@ -1639,9 +1639,9 @@ begin
       csr.mie_mei          <= '0';
       csr.mie_mti          <= '0';
       csr.mie_firq         <= (others => '0');
-      csr.mtvec            <= (others => '0');
+      csr.mtvec            <= CPU_BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit aligned boot address
       csr.mscratch         <= x"19880704";
-      csr.mepc             <= (others => '0');
+      csr.mepc             <= CPU_BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit aligned boot address
       csr.mcause           <= (others => '0');
       csr.mtval            <= (others => '0');
       csr.mtinst           <= (others => '0');
@@ -1657,7 +1657,7 @@ begin
       csr.dcsr_step        <= '0';
       csr.dcsr_prv         <= priv_mode_m_c;
       csr.dcsr_cause       <= (others => '0');
-      csr.dpc              <= (others => '0');
+      csr.dpc              <= CPU_BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit aligned boot address
       csr.dscratch0        <= (others => '0');
       csr.tdata1_hit_clr   <= '0';
       csr.tdata1_execute   <= '0';
@@ -1677,6 +1677,7 @@ begin
       if (csr.we = '1') then
         case csr.addr is
 
+          -- --------------------------------------------------------------------
           -- machine trap setup --
           -- --------------------------------------------------------------------
           when csr_mstatus_c => -- machine status register
@@ -1712,6 +1713,7 @@ begin
               end if;
             end if;
 
+          -- --------------------------------------------------------------------
           -- machine trap handling --
           -- --------------------------------------------------------------------
           when csr_mscratch_c => -- machine scratch register
@@ -1729,6 +1731,7 @@ begin
           when csr_mip_c => -- machine interrupt pending
             csr.mip_firq_nclr <= csr.wdata(31 downto 16); -- set low to clear according bit (FIRQs only)
 
+          -- --------------------------------------------------------------------
           -- machine counter setup --
           -- --------------------------------------------------------------------
           when csr_mcountinhibit_c => -- machine counter-inhibit register
@@ -1752,6 +1755,7 @@ begin
               csr.minstretcfg_uinh <= csr.wdata(28);
             end if;
 
+          -- --------------------------------------------------------------------
           -- debug mode CSRs --
           -- --------------------------------------------------------------------
           when csr_dcsr_c => -- debug mode control and status register
@@ -1777,6 +1781,7 @@ begin
               csr.dscratch0 <= csr.wdata;
             end if;
 
+          -- --------------------------------------------------------------------
           -- trigger module CSRs --
           -- --------------------------------------------------------------------
           when csr_tdata1_c => -- match control
@@ -1798,6 +1803,7 @@ begin
               end if;
             end if;
 
+          -- --------------------------------------------------------------------
           -- not implemented (or implemented externally) --
           -- --------------------------------------------------------------------
           when others => NULL;
@@ -1944,6 +1950,7 @@ begin
     csr_rdata <= (others => '0'); -- default
     case csr.raddr is
 
+      -- --------------------------------------------------------------------
       -- machine trap setup --
       -- --------------------------------------------------------------------
       when csr_mstatus_c => -- machine status register - low word
@@ -1986,11 +1993,13 @@ begin
           end if;
         end if;
 
+      -- --------------------------------------------------------------------
       -- machine configuration --
       -- --------------------------------------------------------------------
 --    when csr_menvcfg_c  => csr_rdata <= (others => '0'); -- hardwired to zero
 --    when csr_menvcfgh_c => csr_rdata <= (others => '0'); -- hardwired to zero
 
+      -- --------------------------------------------------------------------
       -- machine trap handling --
       -- --------------------------------------------------------------------
       when csr_mscratch_c => -- machine scratch register
@@ -2015,6 +2024,7 @@ begin
       when csr_mtinst_c => -- machine trap instruction
         csr_rdata <= csr.mtinst;
 
+      -- --------------------------------------------------------------------
       -- machine counter setup --
       -- --------------------------------------------------------------------
       when csr_mcountinhibit_c => -- machine counter-inhibit register
@@ -2058,6 +2068,7 @@ begin
       when csr_mhpmevent14_c => if (hpm_num_c > 11) then csr_rdata <= hpmevent_rd(14); end if;
       when csr_mhpmevent15_c => if (hpm_num_c > 12) then csr_rdata <= hpmevent_rd(15); end if;
 
+      -- --------------------------------------------------------------------
       -- counters and timers --
       -- --------------------------------------------------------------------
       -- low word --
@@ -2094,6 +2105,7 @@ begin
       when csr_mhpmcounter14h_c | csr_hpmcounter14h_c => if (hpm_num_c > 11) then csr_rdata <= cnt_hi_rd(14); end if;
       when csr_mhpmcounter15h_c | csr_hpmcounter15h_c => if (hpm_num_c > 12) then csr_rdata <= cnt_hi_rd(15); end if;
 
+      -- --------------------------------------------------------------------
       -- machine information registers --
       -- --------------------------------------------------------------------
       when csr_mvendorid_c  => csr_rdata <= VENDOR_ID; -- vendor's JEDEC ID
@@ -2102,12 +2114,14 @@ begin
       when csr_mhartid_c    => csr_rdata <= HART_ID; -- hardware thread ID
 --    when csr_mconfigptr_c => csr_rdata <= (others => '0'); -- machine configuration pointer register - hardwired to zero
 
+      -- --------------------------------------------------------------------
       -- debug mode CSRs --
       -- --------------------------------------------------------------------
       when csr_dcsr_c      => if (CPU_EXTENSION_RISCV_Sdext) then csr_rdata <= csr.dcsr_rd;   end if; -- debug mode control and status
       when csr_dpc_c       => if (CPU_EXTENSION_RISCV_Sdext) then csr_rdata <= csr.dpc;       end if; -- debug mode program counter
       when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_Sdext) then csr_rdata <= csr.dscratch0; end if; -- debug mode scratch register 0
 
+      -- --------------------------------------------------------------------
       -- trigger module CSRs --
       -- --------------------------------------------------------------------
 --    when csr_tselect_c => if (CPU_EXTENSION_RISCV_Sdtrig) then csr_rdata <= (others => '0'); end if; -- hardwired to zero = only 1 trigger available
@@ -2119,6 +2133,7 @@ begin
           csr_rdata(15 downto 00) <= x"0006"; -- mcontrol6 type trigger only
         end if;
 
+      -- --------------------------------------------------------------------
       -- NEORV32-specific (RISC-V "custom") read-only CSRs --
       -- --------------------------------------------------------------------
       -- machine extended ISA extensions information --
@@ -2143,6 +2158,7 @@ begin
         csr_rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN);                -- DSP-based multiplication (M extensions only)
         csr_rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN);              -- parallel logic for shifts (barrel shifters)
 
+      -- --------------------------------------------------------------------
       -- undefined/unavailable (or implemented externally) --
       -- --------------------------------------------------------------------
       when others => NULL; -- read as zero

diff --git a/rtl/core/neorv32_cpu_pmp.vhd b/rtl/core/neorv32_cpu_pmp.vhd
@@ -132,7 +132,7 @@ architecture neorv32_cpu_pmp_rtl of neorv32_cpu_pmp is
     fail_rw  : std_ulogic_vector(NUM_REGIONS downto 0);
   end record;
   signal check : check_t;
-  
+
 begin
 
   -- Sanity Checks --------------------------------------------------------------------------

diff --git a/rtl/core/neorv32_crc.vhd b/rtl/core/neorv32_crc.vhd
@@ -123,8 +123,6 @@ begin
     end if;
   end process bus_access;
 
-  -- no access error possible --
-
 
   -- Bit-Serial CRC Core --------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------