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🐛 fix bug in instruction-misaligned exception handling #734

Merged
merged 11 commits into from
Nov 23, 2023
Merged

🐛 fix bug in instruction-misaligned exception handling #734

merged 11 commits into from
Nov 23, 2023

Commits on Nov 21, 2023

  1. [rtl] update version ID

    @stnolting
    stnolting committed Nov 21, 2023
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  2. [processor_check] check that an unaligned JALR destination does not a… 

    …lter the link register
    @stnolting
    stnolting committed Nov 21, 2023
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  3. [changelog] add v1.9.1.4

    @stnolting
    stnolting committed Nov 21, 2023
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  4. [docs] fix mepc value on misaligned instruction

    @stnolting
    stnolting committed Nov 21, 2023
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  5. [!] disable C ext. for processor check 

    to check for correct handling of misaligned instruction exception; C extension is still tested/verified in neorv32-riscof
    @stnolting
    stnolting committed Nov 21, 2023
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  6. [processor_check] minor cleanups

    @stnolting
    stnolting committed Nov 21, 2023
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  7. 🐛 [rtl] fix handling of misaligned instruction exception

    @stnolting
    stnolting committed Nov 21, 2023
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Commits on Nov 22, 2023

  1. [revert] re-enable C in Vunit testbench

    @stnolting
    stnolting committed Nov 22, 2023
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  2. mepc & dpc: hardwire bit 1 to zero if IALIGN = 32 

    i.e. if the C ISA extension is disabled
    @stnolting
    stnolting committed Nov 22, 2023
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Commits on Nov 23, 2023

  1. [sim] commet fix

    @stnolting
    stnolting committed Nov 23, 2023
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  2. [mepc,dpc] mask bit 1 on explicit CSR write if ALIGN = 32

    @stnolting
    stnolting committed Nov 23, 2023
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