[cpu] remove branch prediction logic

[stnolting]

This PR removes the CPU front end 's "branch prediction" logic that was used to halt instruction fetch while a branch/jump instruction is in progress until the destination address is available (resulting in less bus traffic / congestion).

However, benchmarks show that this prediction actually lowers performance:

Exemplary CoreMark run with branch prediction:

NEORV32: Hardware Performance Monitors (low words only)
 > Active clock cycles:          2199671829
 > Retired instructions:         596184106
 > Retired compr. instructions:  349937868
 > Instr.-fetch wait cycles:     34008506
 > Instr.-issue wait cycles:     286243045
 > Multi-cycle ALU wait cycles:  99331050
 > Load operations:              108277848
 > Store operations:             28390960
 > Load/store wait cycles:       5984501
 > Unconditional jumps:          16292334
 > Conditional branches (all):   115064467
 > Conditional branches (taken): 58094389
 > Entered traps:                0
 > Illegal operations:           0

Exemplary CoreMark run without branch prediction:

NEORV32: Hardware Performance Monitors (low words only)
 > Active clock cycles:          2188425528 (faster!)
 > Retired instructions:         596184106
 > Retired compr. instructions:  349937868
 > Instr.-fetch wait cycles:     0
 > Instr.-issue wait cycles:     263816491
 > Multi-cycle ALU wait cycles:  99331050
 > Load operations:              108277848
 > Store operations:             28390960
 > Load/store wait cycles:       17164754
 > Unconditional jumps:          16292334
 > Conditional branches (all):   115064467
 > Conditional branches (taken): 58094389
 > Entered traps:                0
 > Illegal operations:           0

Adding caches results in the same speed up factor when the prediction logic is removed. Additionally, removing the prediction logic reduces core size and relaxes the critical path (= the branch taken / not taken logic).