⚠️ Constrain/optimize MTVAL and MCOUNTEREN CSRs #671
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mtval: The hardware setsmtvalto all-zero if a BREAKPOINT exception is encountered. This is explicitly permitted by the RISC-V priv. spec. and removes some redundancy (and logic):mepcalready points to the trap-causing instruction.mcounteren: The CSRs is now implemented as a single flip-flop. Hence, user-mode access can only be granted for all counter CSRs or denied for all counter CSRs.