Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Remove Zicond ISA extension #670

Merged
merged 6 commits into from
Aug 13, 2023
Merged

Remove Zicond ISA extension #670

merged 6 commits into from
Aug 13, 2023

Conversation

stnolting
Copy link
Owner

@stnolting stnolting commented Aug 12, 2023

The Zicond ISA extension (conditional operations) is removed from the core. It will be re-added when the specification is officially ratified.

Plus minor CPU control rtl cleanups and optimizations.

@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related labels Aug 12, 2023
@stnolting stnolting self-assigned this Aug 12, 2023
@stnolting stnolting marked this pull request as ready for review August 12, 2023 19:59
@stnolting stnolting merged commit 4ce9f7a into main Aug 13, 2023
8 checks passed
@stnolting stnolting deleted the dev120823 branch August 13, 2023 14:47
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

1 participant