[rtl] Cleanups and Optimizations #660
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- GATEWAY: remove IO port's register stages - BUS_SWITCH: less hardware, better timing
stnolting
changed the title
NikLeberg
reviewed
Jul 31, 2023
| @@ -459,23 +458,29 @@ A pending FIRQ has to be explicitly cleared by writing zero to the according <<_ | |||
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| As a 32-bit architecture the NEORV32 can access a 4GB physical address space. By default, this address space is | |||
| split into six main regions. Each region provides specific _physical memory attributes_ ("PMAs") that define | |||
| the access capabilities. | |||
| the access capabilities (`rwxac`; `r` = read permission, `w` = execute permission, `x` - execute permission, | |||
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a typo slipped in here: execute -> write
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Oh, my fault 😅
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-mstrict-alignand-mbranch-cost=10CPU_IPB_ENTRIEStop generic (instruction prefetch buffer depth); this is now configured using a new package constantconstant ipb_depth_c : natural := 2;and is not meant for editing by the use; CoreMark experiments showed that increasing the IPB beyond 2 entries does not bring much (any) benefitneorv32_intercon.vhd)