✨ Add support for RISC-V A ISA extension (atomic memory access)

[stnolting]

This PR provides a first version of the core that supports the RISC-V A ISA extension for atomic memory accesses. The basic idea as well as many of the hardware aspects were triggered by @NikLeberg in #573 (👍).

ℹ️ This is a quite simple/straightforward approach of implementing LR/SC operations. The handling of those operations is done by the memory/bus system instead of the CPU core. More in-depth information can be found at the bottom of this post.

• Only the load-store (lr.w) and store-conditional (sc.w) instructions are supported. The remaining read-modify-write instructions (like amoswap) are not supported and will raise an illegal instruction exception when executed. However, these unsupported instructions can be emulated using LR/SC combinations. An emulation library for the missing AMO operations and an according test program will be provided.
• The A extension is enabled via the new CPU_EXTENSION_RISCV_A processor generic.
• The A instructions are tightly coupled to the memory/bus system of the processor. Besides the CPU-internal logic for executing LR/SC instructions a new bus module ("Reservation Set Control") is added that keeps track of the LR/SC reservation set. (see image below).
• Right now only a single reservation set is supported. The granularity (= "size") of the reservation set is 4 bytes (1 word) by default, but can be customized via a new processor generic (AMO_RVS_GRANULARITY).

More Information

🔍 How do atomic memory accesses / LR/SC combinations work on a hardware level (NEORV32 data sheet)?

• The RISC-V A ISA extension: docs: A ISA Extension
• The reservation set controller: docs: Reservation Set Controller
• The LR/SC bus interface protocol: docs: Bus Interface / Atomic Accesses

💾 How to emulate AMO operations using LR/SC combinations (NEORV32 software framework)?

• The AMO emulation library: sw: neorv32_cpu_amo.c
• An AMO test/example program: sw: sw/example/atomic_test

TODO

The reservation set controller already provides an external interface so other external cores could "snoop" and invalidate the state of the reservation set. However, this interface is not available yet. Maybe this could be integrated into the processor's Wishbone bus... 🤔

[stnolting]

FTR

A extension implemented, documented and tested ✔️
Further links and notes added to initial PR description ✔️