✨ add optional direct memory access controller (DMA)

[stnolting]

This PR adds a first version of the DMA controller proposed in #579.

This is still ⚠️ work-in-progress and highly 🧪 experimental.

• add DMA hardware module
• integrate DMA into processor
  • bus system modifications to shorten critical path (?)
• add DMA HAL (SW library files)
• add DMA test case(s) to processor check program
• add simple DMA example/demo program
• add DMA to documentation
• update SVD file

[stnolting]

This seems to be ready. 🚀

The DMA works as expected (see the demo program output below) and consumes about 1.5x the resources of the default UART.

Example 1: Byte-to-byte block transfer using busy wait
Transfer done.
---------------------------
     SRC         DST
[0]  0x66778899  0x66778899
[1]  0x22334455  0x22334455
[2]  0xaabbccdd  0xaabbccdd
[3]  0x0011eeff  0x0011eeff
---------------------------

Example 2: Word-to-word one-to-many transfer using busy wait
Transfer done.
---------------------------
     SRC         DST
[0]  0x66778899  0x66778899
[1]  0x22334455  0x66778899
[2]  0xaabbccdd  0x66778899
[3]  0x0011eeff  0x66778899
---------------------------

Example 3: Byte-to-signed-word block transfer using transfer-done interrupt
<<DMA interrupt!>>
---------------------------
     SRC         DST
[0]  0x66778899  0xffffff99
[1]  0x22334455  0xffffff88
[2]  0xaabbccdd  0x00000077
[3]  0x0011eeff  0x00000066
---------------------------

I need to do some more analyzes regarding efficiency / bus traffic and regarding the impact on the bus system's critical path. Optimizations might follow in future PRs. 😉