🐛⚠️ CPU bug-fixes, major cleanups and optimizations #586
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stnolting
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Apr 15, 2023
Pass-through the original compressed instruction word if illegal instruction word.
* code cleanup and (area) optimization * fix WFI behavior * add remaining PMP CSRs * rework MTVAL CSR
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🐛 fix bug in behavior of
wfiinstruction: CPU has to wake up from sleep mode if any enabled interrupt source becomes pending; #583, thx @biosbob!🐛 fix bug in XIRQ controller that was introduced with the latest update (rtl typo error); #584, thx @matty0005!
🚀 RISC-V compatibility: add all PMP registers that are defined by the RISC-V spec; i.e. access to
pmpaddr63must not trap and just return zero if that specific PMP region is not implemented; riscv/riscv-isa-manual#1011mtvalCSR: do not put program counter value on instruction misaligned / instruction access fault exceptions into this CSR (redundant; already available inmepc);mtvalwill now also show the faulting instruction word on an illegal instruction exception to simplify emulation - if the illegal instruction trap is caused by a compressed instructionmtvalwill show the according zero-extended compressed instruction word; furthermore,mtvalis now read-only (again)✨ massive RTL code cleanup and (area) optimization of CPU control unit
✨ minor RTE edits; default debug handlers now show additional trap information
(Sorry for putting all this into a single commit/pr 🙈)