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[PMP] add support for NA4 and NAPOT modes #566

Merged
merged 6 commits into from
Apr 1, 2023
Merged

[PMP] add support for NA4 and NAPOT modes #566

merged 6 commits into from
Apr 1, 2023

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stnolting
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@stnolting stnolting commented Apr 1, 2023

  • ✨ add support for NA4 (naturally aligned power-of-two region, 4 byte wide) and NAPOT (naturally aligned power-of-two region, larger than 4 bytes) to the processor's physical memory protection system - PMP is now full spec-compliant
  • ⚠️ change behavior of neorv32_cpu_pmp_configure_region() function

@stnolting stnolting added enhancement New feature or request risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related labels Apr 1, 2023
@stnolting stnolting self-assigned this Apr 1, 2023
@stnolting stnolting changed the title [rtl] PMP: add support for NA4 and NAPOT modes [PMP] add support for NA4 and NAPOT modes Apr 1, 2023
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I am locking for a real-world application to further test the PMP system. A test suite for RISCOF is on its way (riscv-non-isa/riscv-arch-test#284) but this is still work-in-progress. So if anyone has an idea or even a complete test setup, it would be really great if you could share it 👍

@stnolting stnolting marked this pull request as ready for review April 1, 2023 11:28
@stnolting stnolting merged commit 3214f30 into main Apr 1, 2023
@stnolting stnolting deleted the pmp_update branch April 1, 2023 12:55
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