🧪 Add processor data cache

[stnolting]

This PR adds a data cache to the processor - finally 😅

Right now, it provides external generics to configure the number of blocks and the actual block size. The cache is direct-mapped and uses the "write-through" strategy for memory-cache synchronization. Accesses to addresses 0xF0000000 .. 0xFFFFFFFF are always uncached (for memory-mapped IO).

• a MISSED cache read access will fetch the according memory block from main memory
• a HIT cache read access will return data from the cache
• a MISSED cache write access will directly write to main memory (requires 1 additional cycle)
• a HIT cache write access will write to the cache and also to main memory (requires 1 additional cycle)
• an uncached accesses requires 1 additional cycle

The cache is operational but still quite experimental. Feedback is highly welcome 😉