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[rtl] cleanup, reworks and optimization #559

Merged
merged 6 commits into from
Mar 24, 2023
Merged

[rtl] cleanup, reworks and optimization #559

merged 6 commits into from
Mar 24, 2023

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stnolting
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  • cleanup and improve instruction cache (loading a block on a miss is 1 cycle faster)
  • cleanup PMP and counter CSR logic
  • 🔒 fix minor CSR access check issue; accessing base counters like cycle did not trap when Zicntr was disabled
  • ✨ add full support for mcounteren CSR (constrain user-level access to counter CSRs)

@stnolting
[rtl] cleanup & optimize i-cache
e57704e
@stnolting
[rtl] rework control unit
155c515 
* cleanup counter and PMP CSRs
* fix minor bug in base counter CSR check
* add full support for mcounteren CSR
@stnolting
[sw] rework processor check
e14841c
@stnolting
[sim] use external MEM for TB
c30d321
@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related coding-style Related to the HW/SW coding style labels Mar 24, 2023
@stnolting stnolting self-assigned this Mar 24, 2023
@stnolting stnolting marked this pull request as ready for review March 24, 2023 17:09
@stnolting stnolting merged commit d610a0b into main Mar 24, 2023
@stnolting stnolting deleted the csr_reworks branch March 24, 2023 18:31
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coding-style Related to the HW/SW coding style HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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