[rtl] reworks, cleanups and optimizations

[stnolting]

• remove output gate option (FIFO_GATE) of FIFO component
• if the "synchronous read" option of the FIFO component is enabled (FIFO_RSYNC = true) the status flag outputs are also registered
• optimize NEOLED module (smaller size)
• use synchronous FIFO read access for TRNG module
• fixed read access of UART and SPI module (read accesses required two cycles due to sync. FIFO read access; now the read access dealay is back to one cycle)
• using registers above x15 when the E ISA extension is enabled does not raise an exception anymore