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⚠️ Update / rework SPI module #530

Merged
merged 12 commits into from
Mar 4, 2023
Merged

⚠️ Update / rework SPI module #530

merged 12 commits into from
Mar 4, 2023

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stnolting
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This PR is rework/update of the processor's SPI module.

  • ⚠️ change control register layout
  • ⚠️ remove configurable transmissions size, SPI operations are fixed to 8-bit
  • rework interrupt configuration mechanism (new style 😉)
  • improve blockRAM mapping/inference (using FIFO with synchronous read access)

@stnolting stnolting added HW hardware-related optimization Make things faster, smaller and more efficient labels Mar 4, 2023
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stnolting commented Mar 4, 2023 •
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@akaeba Could you have a look at the demo_spi_irq demo program?

@stnolting stnolting marked this pull request as ready for review March 4, 2023 12:47
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akaeba commented Mar 4, 2023

@akaeba Could you have a look at the demo_spi_irq demo program?

yes i can check.

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akaeba commented Mar 4, 2023

Driver is changed, but evaluation in simulator is pending.

akaeba and others added 2 commits March 4, 2023 17:35
@akaeba
[sw/example/demo_spi_irq/main.c]: fix wrong usage of memset, memset a…
52a826f 
…ccepts size in byte, and sizeof returns umber of bytes. No element division necessary.
@stnolting
adjust SPI control register bits
146fca3
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Seems fine now.
Thanks for updating!

@stnolting stnolting merged commit 816137b into main Mar 4, 2023
@stnolting stnolting deleted the spi_update branch March 4, 2023 20:34
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@stnolting @akaeba