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[sw/example/demo_spi_irq]: make read/write data pointer and busy flag… #471

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Jan 6, 2023
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[sw/example/demo_spi_irq]: make read/write data pointer and busy flag… #471

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16 changes: 8 additions & 8 deletions sw/example/demo_spi_irq/drv/neorv32_spi_irq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -53,7 +53,7 @@
void neorv32_spi_init(t_neorv32_spi *self) {

self->uint8IsBusy = 0;
self->uint32Fifo = (uint32_t) neorv32_spi_get_fifo_depth(); // acquire FIFO depth in elements
self->uint16Fifo = (uint16_t) neorv32_spi_get_fifo_depth(); // acquire FIFO depth in elements
self->uint32Total = 0;
self->uint32Write = 0; // write element count
self->uint32Read = 0; // read element count
Expand All @@ -68,8 +68,8 @@ void neorv32_spi_init(t_neorv32_spi *self) {
**************************************************************************/
void neorv32_spi_isr(t_neorv32_spi *self) {

uint32_t uint32Buf; // help variable
uint32_t uint32Lim; // loop limit
volatile uint32_t uint32Buf; // help variable
uint32_t uint32Lim; // loop limit


neorv32_cpu_csr_write(CSR_MIP, ~(1<<SPI_FIRQ_PENDING)); // ack/clear FIRQ
Expand All @@ -91,7 +91,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
break;
}
// write next packet
uint32Lim = min(self->uint32Write+self->uint32Fifo, self->uint32Total);
uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint8_t *) self->ptrSpiBuf)[self->uint32Write];
Expand All @@ -110,7 +110,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
break;
}
// write next packet
uint32Lim = min(self->uint32Write+self->uint32Fifo, self->uint32Total);
uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint16_t *) self->ptrSpiBuf)[self->uint32Write];
Expand All @@ -129,7 +129,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
break;
}
// write next packet
uint32Lim = min(self->uint32Write+self->uint32Fifo, self->uint32Total);
uint32Lim = min(self->uint32Write+self->uint16Fifo, self->uint32Total);
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint32_t *) self->ptrSpiBuf)[self->uint32Write];
Expand Down Expand Up @@ -158,7 +158,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
**************************************************************************/
int neorv32_spi_rw(t_neorv32_spi *self, void *spi, uint8_t csn, uint32_t num_elem, uint8_t data_byte) {

uint32_t uint32Buf; // help variable
volatile uint32_t uint32Buf; // help variable

if ( 0 != self->uint8IsBusy ) {
return 1; // transfer active, no new request
Expand Down
18 changes: 9 additions & 9 deletions sw/example/demo_spi_irq/drv/neorv32_spi_irq.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -54,14 +54,14 @@
// data handle for ISR
typedef struct t_neorv32_spi
{
void* ptrSpiBuf; /**< SPI buffer data pointer */
uint8_t uint8SzElem; /**< Element Size in byte */
uint8_t uint8Csn; /**< SPI chip select channel */
uint16_t uint32Fifo; /**< Number of elements in Fifo */
uint32_t uint32Total; /**< Number of elements in buffer */
uint32_t uint32Write; /**< To SPI core write elements */
uint32_t uint32Read; /**< From SPI core read elements */
uint8_t uint8IsBusy; /**< Spi Core is Busy*/
void* ptrSpiBuf; /**< SPI buffer data pointer */
uint8_t uint8SzElem; /**< Element Size in byte */
uint8_t uint8Csn; /**< SPI chip select channel */
uint16_t uint16Fifo; /**< Number of elements in Fifo */
uint32_t uint32Total; /**< Number of elements in buffer */
volatile uint32_t uint32Write; /**< To SPI core write elements */
volatile uint32_t uint32Read; /**< From SPI core read elements */
volatile uint8_t uint8IsBusy; /**< Spi Core is Busy*/
} t_neorv32_spi;


Expand Down