🐛 [rtl] fix iCache block error bug

[stnolting]

Bug Description

Whenever the instruction cache detects a "miss" it fetches a complete block from main memory. If any address within that block does not assert a bus access ACKNOWLEDGE, or if any address within that block asserts a bus accesses ERROR, the whole cache block is invalidated and the CPU receives an ERROR - regardless of the actually accessed address.

Example:

• CPU jump to address 0x00001008, which triggers an i-cache miss
• the i-cache fetches the according block from memory (starting with address 0x00001000)
• address 0x00001000 asserts an ERROR while all other addresses inside the block assert an ACKNOWLEDGE
• the CPU receives an error because the whole block is treated as fault, even though only the (irrelevant) address 0x00001000 reported an ERROR

A more real-world example:

The same error occurs if the instruction cache is fetching a block from a memory that is smaller than the instruction cache block size: if the block size is configured to 64 bytes and the cache tries to access a "freestanding" memory module that implements 32 bytes (starting at a 64-byte-aligned address) then accesses to the upper 32 byte will result a bus ERROR marking the whole block as "faulty" even if the lower 32 bytes are just fine.

Fix Description

Add an additional status bit to each cache word that shows the bus access status (failed/succeed).