🐛 [rtl] core trap fixes

[stnolting]

• Fix a bug in the core's interrupt system: when in user-mode, interrupts are globally enabled even if mstatus.mie is cleared. Quote from the RISC-V privilege specification:

When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and
globally disabled when xIE=0. Interrupts for lower-privilege modes, w<x, are always globally
disabled regardless of the setting of any global wIE bit for the lower-privilege mode. Interrupts for
higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE
bit for the higher-privilege mode. Higher-privilege-level code can use separate per-interrupt enable
bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege
mode.

• The illegal instruction check for CFU (custom functions unit) is changed: instructions targeting the CFU (using custom-0 or custom-1 opcodes) are not checked for illegal registers when the E ISA extension is enabled (registers above x15).

• Rework the handling of the hardware-based mstatus.mie/mstatus.mpie, mstatus.mprv and privilege stacks.