[rtl] set 'mtval' CSR to zero if illegal instruction exception #409
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This PR modifies the behavior of the
mtvalCSR (trap value register).mtvalis set to zero now. Previously, it was written with the (de-compressed) 32-bit instruction word. However, the faulting instruction word can be retrieved by performing a load operation using themepcCSR as address. Hence, this PR removes certain redundancies to reduce area requirements.✔️ This simplification is explicitly allowed by the RISC-V priv. specs.