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🚀 [docs] add neorv32-verilog repository #400

Merged
merged 5 commits into from
Aug 28, 2022
Merged

🚀 [docs] add neorv32-verilog repository #400

merged 5 commits into from
Aug 28, 2022

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stnolting
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@stnolting stnolting commented Aug 28, 2022

neorv32-verilog

This PR adds some documentation and links for the neorv32-verilog repository, which provides an automated GHDL-based flow to convert a custom NEORV32 configuration into an all-Verilog netlist module file (triggered by #266).

@stnolting stnolting added DOC Improvements or additions to documentation enhancement New feature or request experimental Experimental feature labels Aug 28, 2022
@stnolting stnolting self-assigned this Aug 28, 2022
@stnolting stnolting linked an issue Aug 28, 2022 that may be closed by this pull request
@stnolting stnolting changed the title 🚀 [docs] add neorv32-verilog 🚀 [docs] add neorv32-verilog repository Aug 28, 2022
@stnolting stnolting marked this pull request as ready for review August 28, 2022 09:54
@stnolting stnolting merged commit a5caa8a into main Aug 28, 2022
@stnolting stnolting deleted the neorv32_verilog branch August 28, 2022 13:54
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[idea] add option to convert processor setup to Verilog
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