🧪 [rtl/system_integration] add LiteX core complex wrapper

[stnolting]

This PR add a very first version of the "NEORV32 Core Complex Wrapper" for integration into @enjoy-digital's LiteX SoC builder framework (discussed in #350): rtl/system_integration/neorv32_litex_core_complex.vhd

The wrapper provides a little-endian Wishbone interface, a JTAG interface for the on-chip debugger and a single interrupt request line that is connected to the CPU's "RISC-V machine external interrupt (MTI)".

Right now, four pre-defined core configurations are available: minimal, lite, standard and full. The actual configuration is selected via the CONFIG generic.

The core configuration for the four versions is just a very early draft right now. However, the configurations are defined by a record-of-array structure so they can be customized easily:

  constant configs_c : configs_t := (
    --               minimal   lite    standard  full
    riscv_c      => ( false,   true,    true,    true  ), -- RISC-V compressed instructions 'C'
    riscv_m      => ( false,   true,    true,    true  ), -- RISC-V hardware mul/div 'M'
    riscv_u      => ( false,   false,   false,   true  ), -- RISC-V user mode 'U'
    riscv_zicntr => ( false,   false,   true,    true  ), -- RISC-V standard CPU counters 'Zicntr'
    riscv_zihpm  => ( false,   false,   false,   true  ), -- RISC-V hardware performance monitors 'Zihpm'
    fast_ops     => ( false,   false,   true,    true  ), -- use DSPs and barrel-shifters
    ipb          => ( 2,       2,       4,       8     ), -- instruction prefetch buffer depth, power of two, min 2
    pmp_nr       => ( 0,       0,       0,       8     ), -- number of PMP regions (0..16)
    hpm_nr       => ( 0,       0,       0,       8     ), -- number of HPM counters (0..29)
    icache_en    => ( false,   false,   true,    true  ), -- instruction cache enabled
    icache_nb    => ( 0,       0,       4,       8     ), -- number of cache blocks (lines), power of two
    icache_bs    => ( 0,       0,       128,     256   ), -- size of cache clock (lines) in bytes, power of two
    icache_as    => ( 1,       1,       1,       2     ), -- associativity (1 or 2)
    mtime        => ( false,   true,    true,    true  )  -- RISC-V machine system timers
  );

The configuration-specific parameters are open for discussion and can be updated after merging.