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⚠️ [rtl] rework SLINK module #349

Merged
merged 10 commits into from
Jun 17, 2022
Merged

⚠️ [rtl] rework SLINK module #349

merged 10 commits into from
Jun 17, 2022

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stnolting
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This is just another rework PR that aims to simplify the processor's SLINK module. Furthermore, support for the AXI Stream-compatible T_LAST signals is added.

🚀 New Features

Add stream link "last" signals to indicate end of packet. New top signals:

slink_tx_lst_o : out std_ulogic_vector(7 downto 0); -- last data of packet
slink_rx_lst_i : in  std_ulogic_vector(7 downto 0) := (others => 'L'); -- last data of packet

Example transmission using "last" signal:
stream_link_interface

⚠️ Major Changes

  • removed all "FIFO half full" status flags and interrupt triggers
  • simplified interrupt configuration
  • removed SLINK IRQ register
  • reorganized CTRL and STATUS registers (bits, flag position, memory-mapped addresses)

@stnolting stnolting added enhancement New feature or request HW hardware-related optimization Make things faster, smaller and more efficient labels Jun 16, 2022
@stnolting stnolting self-assigned this Jun 16, 2022
@stnolting stnolting marked this pull request as ready for review June 16, 2022 15:49
@stnolting stnolting merged commit 6c1add9 into main Jun 17, 2022
@stnolting stnolting deleted the simplify_slink_module branch June 17, 2022 04:55
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