[rtl] rework reset system

[stnolting]

This PR reworks the processor's internal reset generator system and also the behavior of the watchdog's "lock" feature.

Reset System

The reset generator system has been split into an external and an internal system. The external reset is triggered by the processor's rstn_i signal while the internal reset is triggered by the processor's rstn_i signal, the watchdog or the on-chip debugger.

Whenever a valid reset request occurs (internal or external) the reset generator ensures that the reset applied to the system is active for at least 4 cycles. Furthermore, the reset applied to system will be release on falling edge of the system clock to avoid metastable situation (= reset is de-asserted during a rising edge). More information can be found in this nice article: https://www.eetimes.com/how-do-i-reset-my-fpga/

Watchdog

The watchdog is now reset by the internal processor reset, which can be triggered via the external hardware reset signal rstn_i, the on-chip debugger or the watchdog itself (system reset on watchdog timeout).

• ⚠️ The watchdog now requires an "access password" in the upper most 16 bits (MSB-aligned) of the data to be written. If the password is incorrect no data will be written to the watchdog control register adn the according bus access will not be acknowledged resulting in a store access fault exception**. The password is hardwired to 0xCA36 and is used by the WDT library functions.