[rtl] add Wishbone output "gating" #344
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Outgoing signals do no change if there is no active Wishbone transaction.
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This is a rather small PR that adds an "operand gating" function to the external Wishbone interface.
All outgoing signals (seen from the processor) will not change at all when there is no active Wishbone access. This might reduce switching activity in the external memory system and makes inspecting Wishbone transactions in simulation much clearer.