[rtl] rework TWI module

[stnolting]

Triggered by the issues found in #339 this PR provides a complete makeover of the TWI module's hardware. These changes do not impact hardware utilization.

✔️ Optimizations and Fixes

• VHDL code clean-up
• fixed problem with synchronization of a new operation (START, STOP, transmission) to the TWI clock
• SDA will be set LOW after a byte transmission to keep the bus claimed
• data is now sampled from the bus right in the center of SCL's high period
• less transmission overhead (faster)

✨ New Features

• add new status flag to the TWI control register to check if the TWI is currently claimed (by the NEORV32 TWI module or by any other controller): bit 29, TWI_CTRL_CLAIMED, read-only; set if the TWI is busy or if SDA and SCL are both low

⚠️ Relevant Changes

• the "START condition executed" interrupt is removed
• the "STOP condition executed" interrupt is removed
• the interrupt will only fire when a byte transmission has completed

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Exemplary TWI operation using the modified module from this PR:

START condition, transfer 0x70, transfer 0xF1, STOP condition. TWI bus is not connected to any device; SDA and SCL are just connected to "pull-up resistors" (-> 'H'); hence, a high level is sampled in the ACK time slot (=NACK). Note the interrupt requests right at the end of each byte transmission.