[rtl] add hardware reset to IO/peripheral devices

[stnolting]

This PR (finally?) adds a dedicated hardware reset to all IO/peripheral devices.

After having too much trouble with hardware-vs-simulation mismatches (recently: #330, #332) it is about time to add a real reset to the IO devices. Lessons learned. 🙈 😅

Current State (pre-PR)

The current setup relies on a pure software reset scheme, where crt0 is responsible for clearing/resetting all IO devices by writing zero to all memory-mapped registers. Clearing the control register of a device (or to be more specific: the control register's enable bit) will disable and reset the device putting it in a defined state.

Proposed State (this PR)

This PR adds a hardware reset to each IO module's interface registers. Module-internal register still do not provide a dedicated hardware reset!

All interface register are set to zero by the hardware reset - including the control register's enable bit, which will cause the rest of the logic (the internal registers that do not have a dedicated reset) to be reset to a defined state.

The crt0 "hardware reset" code is no longer required and is removed. This makes booting slightly faster.

ℹ️ On Quartus Prime 21.1 (targeting a Cyclone IV FPGA) the modifications from this PR have absolutely no impact on device utilization.

TODO

• rtl modifications (add reset)
• update documentation
• remove crt0 IO initialization routine
• check (simulation & on real hardware) that this PR does not break anything
• update pre-built application images (bootloader and blink_led)