⚠️ remove CPU's A ISA extension (atomic memory access)

[stnolting]

This PR removes the RISC-V A ISA extension (atomic memory access) support of the NEORV32. Furthermore, this is a clean-up of the CPU's instruction and data bus interfaces.

Rationale

The NEORV32 A extensions only supports the load-reservate and store-conditional instruction (lr.w, sc.w). None of the atomic memory operations (AMO) are supported.

The load-reservate and store-conditional instructions are not required to implement lock-free mutexes and semaphores (the NEORV32 is a single-core setup without DMA). Furthermore, the "exclusive" memory access concept of the core is quite complex and sets high expectations regarding the memory system. Also see the discussion in #284.

However, atomic or exclusive memory accesses even for multi-core/DMA-system can still be implemented by the memory system via dedicated "reservation stations"

RTL Changes

Major

• the CPU_EXTENSION_RISCV_A CPU and processor top generic is removed; it is also removed from all wrappers and testbenches
• the Wishbone lock signal wb_lock_o is removed from the processor top entity and also from all wrappers and testbenches

Minor

• the i_bus_lock_o and d_bus_lock_o output signals of the CPU top entity are removed
• the i_bus_priv_o and d_bus_priv_o output signals of the CPU top entity are removed and are replaced by a new "global" priv_o output signal
• the i_bus_wdata_o, i_bus_ben_o and i_bus_re_o output signals of the CPU top entity are removed (those signals were hardwired to zero)

[NikLeberg]

Hi @stnolting,
pretty old pr, but I'm wondering what you meant by:

However, atomic or exclusive memory accesses even for multi-core/DMA-system can still be implemented by the memory system via dedicated "reservation stations"

Could you explain what you mean by that? Is there some more terminology such that google finds relevant content? 😀
Or do you mean things like the Peterson's algorithm?

[stnolting]

Hey Nik!

Actually, I was not thinking/talking about a specific algorithm... You can add any features to the memory system that you like. One option might be to implement atomic/locked/exclusive accesses via specific memory modules: Accessing memory location A (load or store) from core 1 could lock an entire memory region until the same core accesses memory location B. While locked, any access to this region from other cores simply fails.

Obviously, this would be a very platform-specific mechanism.