🐛 fix bug in crt0.S interrupt setup

[stnolting]

This PR fixes a bug in the processor startup code sw/common/crt0.S.

Bug Description

Imagine the following scenario:

• We are running the bootloader and want to upload a new program using the on-chip debugger. The bootloader uses the MTI interrupt (machine timer interrupt) for the "heart beat" LED and also for the auto-boot timeout.
• We halt the CPU using openOCD + GDB - so we are starting a debug session. The CPU is halted and the machine timer interrupt will enqueue in the mip CSR.
• We upload the new program and start executing it.
• The crt0 code of the new program problem will (re-)init the stackpointer and will also override the entry point for all exceptions (mtvec) as well as disabling all interrupts.
• However, before all this is tone, the pending machine timer interrupt might kick in.
• At this point the stack might have already been setup for the new program while the exception entry point (mtvec) and all the interrupt configuration have not. Hence, the bootloader's trap handler gets called but with a modified stack that has already been setup for the new program.
• The result is a stack corruption making the CPU crash. 💥

Bug Fix

The very first thing crt0.S has to do is to clear the global interrupts enable flag (mstatus.mie).