[rtl] set mtval CSR to zero on ebreak instructions #289
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
stnolting
added
risc-v compliance
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR modifies the CPU's exception logic.
Whenever a software breakpoint exception is raised (
ebreakorc.ebreakinstruction), the CPU now clearsmtvalCSR. The pre-PR hardware copied the address of the according instruction fromPCintomtval, which is redundant (the address is also available inmepc) and also no longer required to comply with the spec:RISC-V Machine ISA version 1.12:
Since we are using the default riscv-arch-test repo we now need to modify the "golden reference" for the according ISA tests. This is unpretty, but inevitable right now.
In the far future the
isa-testRISC-V architecture tests might be removed and superseded by the new RISCOF-based verification framework.