[rtl] CPU code clean-up; add RISC-V mstatus.TW CSR bit #285
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stnolting
added
risc-v compliance
add user-mode HPM CSR addresses - these are not implemented and are added just for information
- VHDL CPU code clean-ups - add RISC-V mstatus.TW bit
stnolting
changed the title
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This PR is another clean-up and optimization of the CPU's control unit.
✨ Additionally, this PR adds support for the RISC-V
mstatus.TWflag. This flag is is used to control the execution of thewfi(wait for interrupt / sleep) instruction in less-privileged user-mode. When set, executingwfiin user-mode will raise an illegal instruction exception. When cleared, user-mode is allowed to executewfi. If user-mode is not implemented themstatus.TWflag is hardwired to zero.ℹ️ The user-level hardware performance monitor CSRs are added to the hardware in order to simplifiy CSR address decoding. However, the user-level HPM CSRs
hpmcounter*[h]are NOT implemented. Any access from any operation mode will raise an exception. Only machine-mode is allowed to use the HPMs via the dedicatedmhpmcounter*[h]CSRs.