[rtl/core] add 4 additional CPU CP slots; fix bugs in CP arbitration logic #262
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these additional slots are unused right now and are reserved for future (ISA) extensions
* fixed bug in B co-processor * fixed bug in co-processor arbitration when a trap occurs * added four additional (empty) co-processor slots
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This PR adds four additional co-processor slots (4..7) to the CPU's ALU. The new co-processor slots are not used yet and are reserved for future (ISA) extensions. Slot 4 is going to be used to implement a Custom Functions Unit (CFU) that allows to implement custom RISC-V instructions.
With this PR the ALU contains up to eight co-processors:
I/Ebase ISA, mandatoryMISA extension, optionalBISA extension, optionalZfinxISA extensions, optional🐛 This PR also fixes a bug in the co-processor arbitration logic: if a co-processor operation is triggered by an illegal instruction (the instruction itself is fine - it just triggers an illegal/unsupported co-processor function) the according co-processor has to terminate any internal operation that has been incorrectly triggered. Otherwise, an instruction right at the beginning of the illegal instruction trap handler that uses that specific co-processor might get an incorrect co-processor result.
🐛 Another small bug is fixed by this PR: there was an instruction decoding collision in the bit-manipulation co-processor between the
cpopandrolinstructions.