[rtl/core] rework CPU issue engine (area optimization) #256
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stnolting
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This PR provides a rework of the CPU's issue engine to reduce it's resource requirements.
The issue engine is located right between the pipeline front end (instruction fetch and instruction prefetch buffer) and the actual execution unit. The issue engine is responsible for decoding compressed 16-bit instruction (RISC-V
Cextension) and for handling unaligned 32-bit instructions. The changes from this PR highly reduce the size of this engine (~100 LUTs less on an Intel Cyclone IV FPGA). Note: the issue engine is only relevant if theCISA extension is implemented (enabled via theCPU_EXTENSION_RISCV_Cgeneric).Furthermore, this PR includes some minor code clean-up of the CPU's control engine.
✔️ Changes in this PR are fully backwards-compatible.