Add cyclone2 legacy mem-files

CHANGELOG.md

@@ -26,6 +26,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:----------:|:-------:|:--------|
+| 04.11.2021 | 1.6.3.2 | added optional _alternative_ IMEM and DMEM architecture-only design files (in `rtl/core/mem`); these are not device-specific ("cyclone 2") as they do not use any FPGA-specific primitives or macros - just a different HDL style for describing memories is used (see [PR #192](https://github.com/stnolting/neorv32/pull/198) and [Issue #197](https://github.com/stnolting/neorv32/issues/197)) |
 | 03.11.2021 | 1.6.3.1 | :sparkles: added new peripheral module - general purpose 32-bit timer `GPTMR` ([see PR #195](https://github.com/stnolting/neorv32/pull/195)) |
 | 02.11.2021 |[**:rocket:1.6.3**](https://github.com/stnolting/neorv32/releases/tag/v1.6.3) | **New release** |
 | 01.11.2021 | 1.6.2.13 | added new top generics to explicitly control implementation of `Zicntr` (CPU base counters) and `Zihpm` (hardware performance monitors, see [PR #192](https://github.com/stnolting/neorv32/pull/192) |

docs/datasheet/overview.adoc

@@ -193,7 +193,7 @@ neorv32                - Project home folder
 :sectnums:
 === VHDL File Hierarchy
 
-All necessary VHDL hardware description files are located in the project's `rtl/core folder`. The top entity
+All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity
 of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.
 
 [IMPORTANT]
@@ -243,14 +243,14 @@ neorv32_top.vhd                  - NEORV32 Processor top entity
 ├neorv32_wishbone.vhd            - External (Wishbone) bus interface
 ├neorv32_xirq.vhd                - External interrupt controller
 │
-├mem/neorv32_dmem.default.vhd    - _Default_ data memory (architecture-only!)
-└mem/neorv32_imem.default.vhd    - _Default_ instruction memory (architecture-only!)
+├mem/neorv32_dmem.default.vhd    - _Default_ data memory (architecture-only)
+└mem/neorv32_imem.default.vhd    - _Default_ instruction memory (architecture-only)
 ...................................
 
 [NOTE]
 The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:
 a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition
-(`mem/neorv32_*mem.default.vhd`). The **default** architecture definitions from `rtl/core/mem` provide a _generic_ and
+(`mem/neorv32_*mem.default.vhd`). The `*.default.vhd` architecture definitions from `rtl/core/mem` provide a _generic_ and
 _platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture
 source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
 and/or timing.

docs/userguide/content.adoc

@@ -147,8 +147,8 @@ if you instantiate one of the test setups.
 
 .Internal Memories
 [IMPORTANT]
-For a _general_ first setup (technology-independent) use the _default_ memory architectures for the internal memories
-(IMEM and DMEM). These are located in `rtl/core/mem`, so **make sure to add the files from `rtl/core/mem` to your project, too**. +
+For a _general_ first setup (technology-independent) use the `*.default.vhd` memory architectures for the internal memories
+(IMEM and DMEM). These are located in `rtl/core/mem` so make sure to add the files to your project, too. +
  +
 If synthesis cannot efficiently map those default memory descriptions to the available memory resources, you can later replace the
 default memory architectures by optimized platform-specific memory architectures. **Example:** The `setups/radiant/UPduino_v3`

rtl/core/mem/README.md

@@ -0,0 +1,14 @@
+# Processor Memory Source Files
+
+This folder provides the architecture-only VHDL sources for the processor-internal memories
+(instruction memory "IMEM", data memory "DMEM"). Different implementations are available - but
+only **one** version of each (IMEM and DMEM) has to be added as actual source files.
+
+For the first implementation the `*.default.vhd` files should be selected. The HDL style for describing
+memories used by these files have proven **platform-independence** across several FPGA architectures and toolchains.
+
+If synthesis fails to infer actual block RAM resources from these files, try the legacy `*.cyclone2.vhd` file, which
+provide a different HDL style. These files are intended for legacy support of older Intel FPGAs. However, these files
+do **not** use platform-specific macros or primitives - so they might also work for other FPGAs and toolchains.
+
+:warning: Make sure to add the selected files from this folder also to the `neorv32` design library.

rtl/core/mem/neorv32_dmem.cyclone2.vhd

@@ -0,0 +1,130 @@
+-- #################################################################################################
+-- # << NEORV32 - Processor-internal data memory (DMEM) >>                                         #
+-- # ********************************************************************************************* #
+-- # BSD 3-Clause License                                                                          #
+-- #                                                                                               #
+-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
+-- #                                                                                               #
+-- # Redistribution and use in source and binary forms, with or without modification, are          #
+-- # permitted provided that the following conditions are met:                                     #
+-- #                                                                                               #
+-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
+-- #    conditions and the following disclaimer.                                                   #
+-- #                                                                                               #
+-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
+-- #    conditions and the following disclaimer in the documentation and/or other materials        #
+-- #    provided with the distribution.                                                            #
+-- #                                                                                               #
+-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
+-- #    endorse or promote products derived from this software without specific prior written      #
+-- #    permission.                                                                                #
+-- #                                                                                               #
+-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
+-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
+-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
+-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
+-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
+-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
+-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
+-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
+-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
+-- # ********************************************************************************************* #
+-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
+-- #################################################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library neorv32;
+use neorv32.neorv32_package.all;
+
+architecture neorv32_dmem_rtl of neorv32_dmem is
+
+  -- IO space: module base address --
+  constant hi_abb_c : natural := 31; -- high address boundary bit
+  constant lo_abb_c : natural := index_size_f(DMEM_SIZE); -- low address boundary bit
+
+  -- local signals --
+  signal acc_en  : std_ulogic;
+  signal rdata   : std_ulogic_vector(31 downto 0);
+  signal rden    : std_ulogic;
+  signal addr    : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
+  signal addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
+
+  -- -------------------------------------------------------------------------------------------------------------- --
+  -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have         --
+  -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
+  -- -------------------------------------------------------------------------------------------------------------- --
+
+  -- RAM - not initialized at all --
+  signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE/4-1);
+  signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE/4-1);
+  signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE/4-1);
+  signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1);
+
+  -- read data --
+  signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0);
+
+begin
+
+  -- Sanity Checks --------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using CYCLONE-2-optimized HDL style DMEM." severity note;
+  assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) & " bytes)." severity note;
+
+
+  -- Access Control -------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
+  addr   <= addr_i(index_size_f(DMEM_SIZE/4)+1 downto 2); -- word aligned
+
+
+  -- Memory Access --------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  mem_access: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      addr_ff <= addr;
+      if (acc_en = '1') then -- reduce switching activity when not accessed
+        if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0
+          mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00);
+        end if;
+        if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1
+          mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08);
+        end if;
+        if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2
+          mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16);
+        end if;
+        if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3
+          mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24);
+        end if;
+      end if;
+    end if;
+  end process mem_access;
+
+  -- sync(!) read - alternative HDL style --
+  mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr_ff)));
+  mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr_ff)));
+  mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr_ff)));
+  mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr_ff)));
+
+
+  -- Bus Feedback ---------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  bus_feedback: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      rden  <= acc_en and rden_i;
+      ack_o <= acc_en and (rden_i or wren_i);
+    end if;
+  end process bus_feedback;
+
+  -- pack --
+  rdata <= mem_ram_b3_rd & mem_ram_b2_rd & mem_ram_b1_rd & mem_ram_b0_rd;
+
+  -- output gate --
+  data_o <= rdata when (rden = '1') else (others => '0');
+
+
+end neorv32_dmem_rtl;

rtl/core/mem/neorv32_dmem.default.vhd

@@ -69,7 +69,7 @@ begin
 
   -- Sanity Checks --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using default platform-agnostic DMEM." severity note;
+  assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic DMEM." severity note;
   assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) & " bytes)." severity note;