[UARTs] add RX & TX FIFOs

[stnolting]

This PR adds optional and fully configurable RX and TX FIFOs to the UARTs. Furthermore, this PR provides a complete makeover of the UART's VHDL source code (clean-up and logic optimization).

This PR will be merged when implementation & testing are done and documentation is updated.
Any kind of feedback is highly appreciated.

Affected peripheral devices

• UART0 (FIRQ 2, 3)
• UART1 (FIRQ 4, 5)

Old Version (current state, pre-PR)

The current UARTs do not provide any kind of TX buffering and only provide a simple RX double-buffering.

The current UART interrupts:

• TX IRQ: "transmission done", transmitter done sending
• RX IRQ: "receive complete", receiver finished receiving

New Version (this PR)

The new version of the UART provides independent RX and TX FIFOs, which are configured by new generics:

• IO_UART0_RX_FIFO: type natural, depth of UART0 RX FIFO, power of 2, min 1
• IO_UART0_TX_FIFO: type natural, depth of UART0 TX FIFO, power of 2, min 1
• IO_UART1_RX_FIFO: type natural, depth of UART1 RX FIFO, power of 2, min 1
• IO_UART1_TX_FIFO: type natural, depth of UART1 TX FIFO, power of 2, min 1

The FIFO status can be checked by software via six new control register bits (in NEORV32_UARTx.CTRL):

• bit 13, r/-, UART_CTRL_RX_EMPTY - RX FIFO is empty when set
• bit 14, r/-, UART_CTRL_RX_HALF - RX FIFO is at least half-full when set
• bit 15, r/-, UART_CTRL_RX_FULL - RX FIFO is full when set
• bit 16, r/-, UART_CTRL_TX_EMPTY - TX FIFO is empty when set
• bit 17, r/-, UART_CTRL_TX_HALF - TX FIFO is at least half-full when set
• bit 18, r/-, UART_CTRL_TX_FULL - TX FIFO is full when set

Furthermore, the interrupt-trigger can be configured by two new control register bits (in NEORV32_UARTx.CTRL):

• bit 29, r/w, UART_CTRL_RX_IRQ - RX IRQ trigger: 1 = FIFO at least half-full; 0 = FIFO not empty
• bit 30, r/w, UART_CTRL_TX_IRQ - TX IRQ trigger: 1 = FIFO less than half-full; 0 = FIFO not full

✔️ Backwards Compatibility

The changes in this PR are fully backwards-compatible.

The updated software drivers now check the TX FIFO FULL flag (UART_CTRL_TX_FULL) before writing new data. Drivers for reading data from the UART are not altered (UART_DATA_AVAIL is now driven by the RX FIFO instead by the receiver status).

Legacy drivers can still check the transmitter busy flag (UART_CTRL_TX_BUSY) before sending new data (this will just not make use of the TX FIFO capabilities) (looking at @henrikbrixandersen and zephyrproject-rtos/zephyr#39162 😉).

The ressource requirements with FIFO sizes = 1 are identical to the pre-PR version (providing true double-buffering for RX and now also for TX).

[henrikbrixandersen]

@stnolting Sorry I didn't respond to this earlier. This looks like a really nice addition. I will add Zephyr support for using the FIFOs.

[stnolting]

Awesome! 👍