Adding NEORV32 Qsys/Platform Designer component and AvalonMM Master Interface wrapper

[torerams]

This PR is adding a NEORV32 wrapper so that the NEORV can be used as a component (Nios II replacement) in Qsys/Platform Designer designs.
As an example I have added control of some parameters in the Platform Designer GUI.

This makes is simple to configure the NEORV32 and to connect other modules to the CPU.
There is some documentation the Qsys/Platform Designer solution:
https://github.com/torerams/neorv32/tree/qsys_component/rtl/system_integration/neorv32_qsys_component

The PR also include a simple AvalonMM Master Interface wrapper for people wanting a pure VHDL solution outside the Qsys/Platform Designer solution, but still have a standard AvalonMM Master Interface.

The PR also contains 2 new demo setups. One for the Qsys/Platform Designer solution, and one for the AvalonMM wrapper. Both demo designs running on the Terasic DE0-Nano FPGA Board. The demo designs and documentation are heavily based on the de0-nano-test-setup design.
https://github.com/torerams/neorv32/tree/qsys_component/setups/quartus/de0-nano-test-setup-qsys
https://github.com/torerams/neorv32/tree/qsys_component/setups/quartus/de0-nano-test-setup-avalonmm-wrapper

I have tried not to change the files already in the repository, and have only changed the setups/README.md file.
Hope this code can be useful for others.

[stnolting]

Wow, this is really amazing! Thank you so much for your contribution! 👍

I will check out your files - but I am not very experienced (yet) with QSYS. However, there are two things I would like to address here:

1. The rtl folder should be rtl-only - so plain HDL files only. Could you move your QSYS component from rtl/system_integration/neorv32_qsys_component to the setups folder? I think both of your provided setups share the same QSYS component, right? So maybe we could add another "setup" and use that as shared/common QSYS component (like setups/quartus/de0-nano-qsys-common)?
2. We are currently reworking the NEORV32 internal memories / VHDL files ([rtl/core] split dmem/imem entities and architectures to separated files #151). I would like to merge that PR first and then update this one if this is ok with you.

Again, thanks for your work! It is highly appreciated! 🚀

[torerams]

I agree with both your wanted changes.

For 1) I will move the Qsys component to setups/quartus that is a better place for this module.
The Qsys component is a general "module" for any Intel FPGA / Quartus design, so I would like to keep the name "neorv32_qsys_component" and not use any de0-nano specific name.

I will rebase and update to fit the new IMEM/DMEM solution once that solution is merged.

For your info the AvalonMM example design does not use the Qsys component.
It uses a pure VHDL wrapper file that is outside the scope of the Qsys work.
(I considered making 2 PR, but went for 1 PR for both solutions)

[stnolting]

For 1) I will move the Qsys component to setups/quartus that is a better place for this module.
The Qsys component is a general "module" for any Intel FPGA / Quartus design, so I would like to keep the name "neorv32_qsys_component" and not use any de0-nano specific name.

👍

I will rebase and update to fit the new IMEM/DMEM solution once that solution is merged.

Thank you very much ;)

For your info the AvalonMM example design does not use the Qsys component.
It uses a pure VHDL wrapper file that is outside the scope of the Qsys work.
(I considered making 2 PR, but went for 1 PR for both solutions)

Oh, ok. I haven't looked at all new files yet.

[rafaelcorsi]

Hi there, I am new to this project but I work with the qsys and its ecosystem. Can I help this port in any way? all the best.

[stnolting]

Hey @rafaelcorsi
I am no expert when it comes to QSYS and friends 😅
I am thankful for any further help here. Let's first update this PR (#152 (comment)). After that is done it would be great to have some additional feedback / testing here. 👍

[saturn77]

I am willing to test this new Qsys component on the DE10-Nano board. This is an exciting project and a very valuable development for Qsys support! Thanks, James

[stnolting]

I am willing to test this new Qsys component on the DE10-Nano board. This is an exciting project and a very valuable development for Qsys support! Thanks, James

Great to hear! Thank you very much 👍

[torerams]

I have updated the PR:

• Rebased to latest including the imem/dmem split PR
• Changed design to use the new imem/dmem split
• Moved the Qsys component to setups/quartus/neorv32_qsys_component
• Updated documentation and links

Hopefully the PR is ready to be merged.

@saturn77 and @rafaelcorsi, very good if you could help test this, and any feedback would be appreciated.
There is a demo example in setups/quartus/de0-nan-test-setup-qsys for the DE0-Nano board.

I have just added some parameters (that I use) to the Platform Designer GUI, but any/all parameters in the Generic section of NEORV32 could be added to the GUI.

[stnolting]

Look awesome! I really like the detailed READMEs 😄 👍
Keep up your great work!