[setups/osflow] cleanup

.github/generate-job-matrix.py

@@ -2,11 +2,11 @@
 
 print('::set-output name=matrix::' + str([
 {
-  'board': 'UPduino_v3',
+  'board': 'UPduino',
   'design': 'MinimalBoot',
   'bitstream': 'neorv32_UPduino_v3_MinimalBoot.bit'
 }, {
-  'board': 'UPduino_v3',
+  'board': 'UPduino',
   'design': 'UP5KDemo',
   'bitstream': 'neorv32_UPduino_v3_UP5KDemo.bit'
 }, {

setups/examples/Makefile

@@ -7,9 +7,10 @@ TASK := clean $(BITSTREAM)
 
 FOMU_REV ?= pvt
 OrangeCrab_REV ?= r02-25F
+UPduino_REV ?= v3
 
 ifndef BOARD
-$(error BOARD needs to be set to 'Fomu' or 'UPDuino_v3'!)
+$(error BOARD needs to be set to 'Fomu', 'iCESugar', 'UPDuino' or 'OrangeCrab' !)
 endif
 
 run:
@@ -43,9 +44,9 @@ iCESugar:
 	  BITSTREAM=neorv32_$(BOARD)_$(DESIGN).bit \
 	  run
 
-UPduino_v3:
+UPduino:
 	$(MAKE) \
-	  BITSTREAM=neorv32_$(BOARD)_$(DESIGN).bit \
+	  BITSTREAM=neorv32_$(BOARD)_$(UPduino_REV)_$(DESIGN).bit \
 	  run
 
 OrangeCrab:

setups/examples/neorv32_UPduino_v3_BoardTop_MinimalBoot.vhd → setups/examples/neorv32_UPduino_BoardTop_MinimalBoot.vhd

@@ -39,7 +39,7 @@ use ieee.numeric_std.all;
 library iCE40;
 use iCE40.components.all; -- for device primitives and macros
 
-entity neorv32_UPduino_v3_BoardTop_MinimalBoot is
+entity neorv32_UPduino_BoardTop_MinimalBoot is
   port (
     -- UART (uart0) --
     uart_txd_o : out std_ulogic;
@@ -51,7 +51,7 @@ entity neorv32_UPduino_v3_BoardTop_MinimalBoot is
   );
 end entity;
 
-architecture neorv32_UPduino_v3_BoardTop_MinimalBoot_rtl of neorv32_UPduino_v3_BoardTop_MinimalBoot is
+architecture neorv32_UPduino_BoardTop_MinimalBoot_rtl of neorv32_UPduino_BoardTop_MinimalBoot is
 
   -- configuration --
   constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz

setups/examples/neorv32_UPduino_v3_BoardTop_UP5KDemo.vhd → setups/examples/neorv32_UPduino_BoardTop_UP5KDemo.vhd

@@ -39,7 +39,7 @@ use ieee.numeric_std.all;
 library iCE40;
 use iCE40.components.all; -- for device primitives and macros
 
-entity neorv32_UPduino_v3_BoardTop_UP5KDemo is
+entity neorv32_UPduino_BoardTop_UP5KDemo is
   port (
     -- UART (uart0) --
     uart_txd_o  : out std_ulogic;
@@ -65,7 +65,7 @@ entity neorv32_UPduino_v3_BoardTop_UP5KDemo is
   );
 end entity;
 
-architecture neorv32_UPduino_v3_BoardTop_UP5KDemo_rtl of neorv32_UPduino_v3_BoardTop_UP5KDemo is
+architecture neorv32_UPduino_BoardTop_UP5KDemo_rtl of neorv32_UPduino_BoardTop_UP5KDemo is
 
   -- configuration --
   constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz

setups/osflow/boards/index.mk

@@ -14,23 +14,23 @@ FOMU_REV ?= pvt
 ifeq ($(FOMU_REV),evt1)
 YOSYSFLAGS  ?= -D EVT=1 -D EVT1=1 -D HAVE_PMOD=1
 PNRFLAGS    ?= --up5k --package sg48
-CONSTRAINTS ?= $(PCF_PATH)/fomu-evt2.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-evt2.pcf
 else ifeq ($(FOMU_REV),evt2)
 YOSYSFLAGS  ?= -D EVT=1 -D EVT2=1 -D HAVE_PMOD=1
 PNRFLAGS    ?= --up5k --package sg48
-CONSTRAINTS ?= $(PCF_PATH)/fomu-evt2.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
 else ifeq ($(FOMU_REV),evt3)
 YOSYSFLAGS  ?= -D EVT=1 -D EVT3=1 -D HAVE_PMOD=1
 PNRFLAGS    ?= --up5k --package sg48
-CONSTRAINTS ?= $(PCF_PATH)/fomu-evt3.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
 else ifeq ($(FOMU_REV),hacker)
 YOSYSFLAGS  ?= -D HACKER=1
 PNRFLAGS    ?= --up5k --package uwg30
-CONSTRAINTS ?= $(PCF_PATH)/fomu-hacker.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
 else ifeq ($(FOMU_REV),pvt)
 YOSYSFLAGS  ?= -D PVT=1
 PNRFLAGS    ?= --up5k --package uwg30
-CONSTRAINTS ?= $(PCF_PATH)/fomu-pvt.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
 else
 $(error Unrecognized FOMU_REV value. must be "evt1", "evt2", "evt3", "pvt", or "hacker")
 endif
@@ -43,19 +43,21 @@ endif
 ifeq ($(BOARD),iCESugar)
 $(info Setting constraints and implementation args for BOARD iCESugar)
 
-CONSTRAINTS ?= $(PCF_PATH)/iCESugar.pcf
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf
 PNRFLAGS    ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
-IMPL        ?= neorv32_iCESugar_$(ID)
+IMPL        ?= neorv32_$(BOARD)_$(ID)
 
 endif
 
 
-ifeq ($(BOARD),UPduino_v3)
+ifeq ($(BOARD),UPduino)
 $(info Setting constraints and implementation args for BOARD UPduino)
 
-CONSTRAINTS ?= $(PCF_PATH)/UPduino_v3.pcf
+UPduino_REV ?= v3
+
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)_v3.pcf
 PNRFLAGS    ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
-IMPL        ?= neorv32_UPduino_v3_$(ID)
+IMPL        ?= neorv32_$(BOARD)_$(UPduino_REV)_$(ID)
 
 endif
 
@@ -65,8 +67,10 @@ $(info Setting constraints and implementation args for BOARD OrangeCrab)
 
 DEVICE_SERIES = ecp5
 
-CONSTRAINTS ?= $(PCF_PATH)/OrangeCrab.lpf
+OrangeCrab_REV ?= r02-25F
+
+CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf
 PNRFLAGS    ?= --25k --package CSFBGA285 --ignore-loops --timing-allow-fail
-IMPL        ?= neorv32_OrangeCrab_r02-25F_$(ID)
+IMPL        ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(ID)
 
 endif